upd70f3402 Renesas Electronics Corporation., upd70f3402 Datasheet - Page 492

• Manufacturer Part Number: upd70f3402
• Description: 32-/16-bit Single-chip Microcontroller With Can Interface
• Manufacturer: Renesas Electronics Corporation.

(2)
1.
2.
3.
4.
5.
6.
7.
Remark:
492
CSIB
Single Buffer Transfer Mode (Master Mode, Receive Only Mode)
MSB first (DIR = 0), no INTC3nI delay (CSIT = 0), transmission wait disabled (CSWE = 0), CS
inactive disabled (CSMD = 0), CKP = 0, DAP = 1, transmission data length of 8 bits
(CCL[3:0] = [1,0,0,0]), active levels of all chip selects set to “active low”:
Set the CSIM register's POWER bit to 1 to enable the supply of the Queued CSI operation clock.
Set the CSIC and CSIL registers to specify the transfer mode.
Write “1” in the SFA register's FPCLR bit to clear all FIFO pointers.
Specify the transfer mode using the CSIM register's TRMD, DIR, and CSIT bits; at the same time,
set the CRXE bit to 1 to enable the receive operation.
Make sure that the SFA register's SFFUL bit is set to 0, then write chip-select data and dummy
transmission data in the SFCS and SFDB registers in this order (start-of-receive trigger).
Check for a reception to be completed (e.g. by monitoring the INTC3nI interrupt). If so, read the
SIRB register.
Repeat steps (5) and (6) until the last element is received and read from the SIRB register.
Set the CSIM register's CRXE bit to 0 to disable the receive operation (end of receive operation).
SFDB write
CSIBUF_1
CSIBUF_2
CSIBUF_0
UF-empty
SIRB read
CS3n[3:0]
INTC3nI
SFP3-0
CRXE
SCK3
CSOT
SIRB
(1)
The SO3 pin is invalid and maintains its signal level, as the output latch is disabled.
Figure 14-26: Single Buffer Transfer Mode (Master, Receive Only) Timing
SI
(2)(3)
"active-L"
0
(4)
(5)
0
1
dummy
1
0
(5)
Chapter 14 Queued CSI (CSI30, CSI31)
1
CS 0
2
dummy
0
1
Wait insertion by SIRB-full before
INTC3nI/SIRB store/CSOT clear
User’s Manual U16702EE3V2UD00
0
1
1
1
55H
0
1
CS 1
0
1
0
1
0
(6)
0
Wait insertion
by CSIBUF-empty
AAH
(5)
dummy
1
1 1
0 0
(6)
CS 2
1 1
0
0
0
(6)
CCH
(7)