upd70f3402 Renesas Electronics Corporation., upd70f3402 Datasheet - Page 447

• Manufacturer Part Number: upd70f3402
• Description: 32-/16-bit Single-chip Microcontroller With Can Interface
• Manufacturer: Renesas Electronics Corporation.

13.7.5 Continuous reception mode (error)
Figure 13-13 shows the transfer timing when data is transferred with the MSB first (CBnDIR bit of
CBnCTL0 register = 0), when continuous transfer mode (CBnTMS bit of CBnCTL0 register = 1), when
the CBnCKP bit of the CBnCTL1 register = 0, when the CBnDAP bit of the CBnCTL1 register = 1, and
when the transfer data length is 8 bits (CBnCL3 to CBnCL0 bits of the CBnCTL2 register = 0, 0, 0, 0).
(1)
(2)
(3)
(4)
(5)
(6)
(7)
(8)
(9)
(10) Confirm that the CBnTSF bit of the CBnSTR register = 0. Clear the CBnPWR bit to 0 and stop
Clear the CBnPWR bit of the CBnCTL0 register.
Specify the transfer mode by setting the CBnCTL1 and CBnCTL2 registers.
Specify the transfer mode by using the CBnDIR bit of the CBnCTL0 register and, at the same time,
enable reception by setting the CBnRXE bit of the CBnCTL0 register to 1.
Enable CSIB operating clock supply by setting the CBnPWR bit of the CBnCTL0 register to 1.
Read dummy data from the CBnRX register (reception start trigger).
The reception complete interrupt request signal (INTCBnR) is generated to inform the CPU that
the CBnRX (CBnRXL) register can be read.
If the data cannot be read before the next transfer is completed, the CBnOVE flag of the CBnSTR
register is set on completion of reception, and the reception complete interrupt request signal
(INTCBnR) is generated. Read the CBnRX register before the next receive data arrives.
Confirm that the CBnOVE bit = 1, in the INTCBnR interrupt processing, and perform overrun error
processing.
Clear the CBnOVE bit to 0.
clock supply to CSIB.
INTCBnR
CBnOVE
CBnTSF
SCKBn
CBnRX
register
SIBn
Shift
(1) - (4)
Figure 13-13: Continuous Transfer Timing (Error)
(5)
Chapter 13 3-Wire Serial Interface (CSIB)
0
User’s Manual U16702EE3V2UD00
1
0
1
0
1
0
(6)
1
55H
1
0
1
55H
0
1
0
1
(7)+(8)
0
AAH 00H
AAH
(9)
(10)
00H
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