upd70f3402 Renesas Electronics Corporation., upd70f3402 Datasheet - Page 523

• Manufacturer Part Number: upd70f3402
• Description: 32-/16-bit Single-chip Microcontroller With Can Interface
• Manufacturer: Renesas Electronics Corporation.

15.5.2 Fixed channel transfer mode
In “Fixed Channel” transfer mode, the DMA releases the bus after each transfer, but continues to repeat
the DMA transfer until the transfer counter is cleared to 0 without requiring a new DMA transfer request.
When the DMA has released the bus, if another higher priority DMA transfer request is issued, the
higher priority DMA request does not take precedence.
A “Fixed Channel” transfer mode example is shown in Figure 15-15 and 15-16.
In Figure 15-15, DMA channel 0 and 3 are set to “Fixed Channel” transfer mode, with DMBC0 and
DMBC3 set to 2 at the beginning (transfer counter 3).
Figure 15-16 shows also “Fixed Channel” transfer, but with 3 DMA transfers active. DMBC4 is set to 2,
while DMBC2 and DMBC0 are set as 1 (2 transfers):
The DMA controller executes and completes the DMA first transfer (channel 4) before it checks which of
the remaining pending DMA transfer requests has the highest priority. It executes and completes that
DMA transfer (channel 0) before the DMA transfer with the lowest priority is handled.
DMMRQ0
DMMRQ3
INTDMA3
INTDMA0
DMMRQ0
DMMRQ2
DMMRQ4
INTDMA2
INTDMA4
INTDMA0
Note: The bus is always released.
Note: The bus is always released.
Figure 15-16: Fixed Channel Transfer Mode Example (3 Channels)
CPU
CPU
Figure 15-15: Fixed Channel Transfer Example (2 Channels)
CPU DMA3
<1>
CPU DMA4
<1>
<1>
<1>
Chapter 15 DMA Functions (DMA Controller)
Note
User’s Manual U16702EE3V2UD00
Note
CPU DMA3 CPU DMA3
CPU DMA4 CPU DMA4
<2>
<1>
<1>
<2>
Note
Note
<3>
<1>
<1>
Note
Note
CPU
CPU
DMA0 CPU DMA0
DMA0 CPU DMA0
<2>
<2>
Note
Note
<2>
<2>
Note
Note
CPU
CPU
DMA0
DMA2
<2>
<3>
CPU
CPU
DMA2
CPU
<3>
CPU
CPU
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