L64105 LSI Logic Corporation, L64105 Datasheet - Page 95

• Manufacturer Part Number: L64105
• Description: Mpeg-2 Audio/video Decoder
• Manufacturer: LSI Logic Corporation

Figure 4.9
Figure 4.10
Reg. 10
Reg. 11
Reg. 12
Reg. 13
Reg. 14
Reg. 15
Reg. 16
Reg. 9
MSB
MSB
LSB
LSB
Registers 9–12 (0x009–0x00C) SCR Value [31:0]
Registers 13–16 (0x00D–0x010) SCR Compare/Capture [31:0]
7
7
These registers contain the current value of the System Clock Reference
(SCR) Counter. The host must read Register 9, the LSB, first. This
captures the upper 24 bits and writes them into Registers 10, 11, and
12. The host must set the SCR Pause bit in Register 8 before writing to
these registers.
At reset, these registers are initialized to 0xFFFF.FFFF. They can be
configured in two ways. If the SCR Compare/Capture Mode in Register
17 is set to 0b10, the host can write in any value to generate an interrupt
when the SCR Counter reaches that value.
If the SCR Compare/Capture Mode is set to 0b01, the L64105 captures
the SCR Counter value at an event specified by the host and writes the
SCR value to these registers. The capture can be triggered when any
one of the bits in Registers 17 or 18 is set and the corresponding event
occurs.
Host Interface Registers
SCR Compare/Capture [23:16]
SCR Compare/Capture [31:24]
SCR Compare/Capture [15:8]
SCR Compare/Capture [7:0]
SCR Value [23:16]
SCR Value [31:24]
SCR Value [15:8]
SCR Value [7:0]
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
0
0
4-13