L64105 LSI Logic Corporation, L64105 Datasheet - Page 210

• Manufacturer Part Number: L64105
• Description: Mpeg-2 Audio/video Decoder
• Manufacturer: LSI Logic Corporation

6.3.3 PES Packet Structure
6-14
Table 6.9
The read and write pointer registers each contain 20 bits. The most
significant bit is set when the pointer wraps around to the beginning of
the buffer and cleared when the host next reads the register. The next
19 bits are the actual address on 64-bit boundaries since SDRAM
operations are always in bursts of four 16-bit words.
The Audio Decoder and the S/P DIF (IEC958) Formatter both read from
the Audio ES channel buffer so a read pointer is maintained for both; the
Audio ES Channel Buffer Read Address and the S/P DIF Channel Buffer
Read Address.
The number of items (64-bit words) remaining to be read in each of these
buffers is written to the registers listed in Table 6.10 and available to the
host. Again, only the LSB registers are continually updated. The Next
and MSB registers are updated when the host reads the LSB.
Table 6.10
Since the Preparser strips headers out of packets in system and
transport stream modes, it is useful to look at a PES packet before
discussing those modes.
Channel Interface
Pointer
Video ES Channel Buffer Write Address
Audio ES Channel Buffer Write Address
Video ES Channel Buffer Read Address
Audio ES Channel Buffer Read Address
S/P DIF Channel Buffer Read Address
Buffer No. of Items
Video Channel Numitems
Audio Channel Numitems
S/P DIF Channel Numitems
Buffer Write and Read Pointer Registers in ES Mode
Number of Items in Buffers in ES Mode
Figure 6.7
Registers
134–136
137–139
140–142
shows the packet structure. The
Registers
108–110
111–113
120–122
99–101
96–98
Page Ref.
4-32
4-33
4-33
Page Ref.
4-26
4-26
4-27
4-28
4-30