L64105 LSI Logic Corporation, L64105 Datasheet - Page 302

• Manufacturer Part Number: L64105
• Description: Mpeg-2 Audio/video Decoder
• Manufacturer: LSI Logic Corporation

9.3.2 Horizontal Timing
Figure 9.5
(Odd/Not Even)
9-10
HS
VS
VS
Sync Input Timing
Note: Active low mode shown. The even field is detected at the first HS after the VS.
New odd field
Figure 9.5
The polarity of the VS and HS inputs on which the L64105 reacts is
programmable with the Sync Active Low bit in Register 284
Also when the VSYNC Input Type bit in Register 284
the VS input is used as an Even/Not Odd Field indicator. When the bit is
cleared, VS is used as a sync pulse.
The horizontal timing parameters are measured in terms of device clocks
(81 MHz), with the leading edge of horizontal sync corresponding to a
horizontal count of zero. The leading edge of the horizontal sync input
initializes both the horizontal count and the pixel state (pel state) value
as shown in
determining whether luma or chroma data is output onto the pixel data
bus. Since there are four pel components (Cb, Y, Cr, Ys) of the video
stream, the period of the horizontal sync signal should be modulo 4, thus
preventing discontinuity in the pixel data output. For NTSC and PAL
systems, this period is typically 1716 and 1728 device clocks,
respectively.
Video Interface
illustrates the timing of the horizontal and vertical sync inputs.
Figure
9.6. Pel state is an internal control value for
New even field
(page
(page
4-68) is set,
4-67).