L64105 LSI Logic Corporation, L64105 Datasheet - Page 107

• Manufacturer Part Number: L64105
• Description: Mpeg-2 Audio/video Decoder
• Manufacturer: LSI Logic Corporation

Figure 4.29
Figure 4.30
Reg. 88
Reg. 89
Reg. 90
Reg. 91
MSB
MSB
LSB
LSB
Registers 88 and 89 (0x058 and 0x059) Audio PES Header/System
Channel Buffer Start Address [13:0]
Registers 90 and 91 (0x05A and 0x05B) Audio PES Header/System
Channel Buffer End Address [13:0]
7
7
Reserved
Reserved
address. The Memory Interface of the L64105 converts the address to
an SDRAM address at a 256-byte boundary in SDRAM. This register
should only be updated while the channel is stopped (reset).
Registers 84–87 (0x054–0x057) Reserved
These registers allow the host to program the Audio PES Header/System
channel buffer start address. The address is entered as if it were the
upper 14 bits of a 21-bit address for a conventional 2M x 16 RAM
address. The Memory Interface of the L64105 converts the address to
an SDRAM address at a 256-byte boundary in SDRAM. This register
should only be updated while the channel is stopped (reset).
These registers allow the host to program the Audio PES Header/System
channel buffer end address. The address is entered as if it were the
upper 14 bits of a 21-bit address for a conventional 2M x 16 RAM
address. The Memory Interface of the L64105 converts the address to
an SDRAM address at a 256-byte boundary in SDRAM. This register
should only be updated while the channel is stopped (reset).
Registers 92–95 (0x05C–0x05F) Reserved
Video Decoder Registers
6
6
Audio PES Header/System Channel Buffer Start Address [7:0]
Audio PES Header/System Channel Buffer End Address [7:0]
5
5
Audio PES Header/System Channel Buffer End Address [13:8]
Audio/System PES Buff Start Address [13:8]
R/W
R/W
R/W
R/W
0
0
[7:0]
[7:0]
4-25