L64105 LSI Logic Corporation, L64105 Datasheet - Page 233

• Manufacturer Part Number: L64105
• Description: Mpeg-2 Audio/video Decoder
• Manufacturer: LSI Logic Corporation

Figure 7.3
DQ[15:0]
Figure 7.4
81 MHz
7.4 SDRAM Refresh and Arbitration
SRASn
SCASn
81 MHz
SWEn
SRASn
SCASn
A[10:0]
SCSn
SWEn
SCSn
ref
SDRAM Timing Requirements for Writes
SDRAM Timing Requirements for Refresh
act0
row
0
0
T
RCD
The refresh rate of the SDRAM is sufficient to maintain 2048 refresh
cycles/32 ms. The number of refreshes per macroblock is set by the
Refresh Extend bits in Register 193
refreshes per macroblock is sufficient. More refreshes are excessive and
the setting of 1 is for LSI Logic internal use only.
SDRAM Refresh and Arbitration
read0
col row
CAS Latency
0
T
RAS
act1
1
1
0
0
T
RAS
0
read1
col
1
1
pre0
0
0
0
1
ref
1
1
act0
row
pre1
1
(page
read0
T
T
RP
RAS
col row
0
0
act1
1
1
4-40). The default setting of 2
0
0
read1
0
col
1
1
1
pre0
act
0
0
0
1
1 1
7-5