L64105 LSI Logic Corporation, L64105 Datasheet - Page 112

• Manufacturer Part Number: L64105
• Description: Mpeg-2 Audio/video Decoder
• Manufacturer: LSI Logic Corporation

Figure 4.39
Figure 4.40
4-30
Reg. 120
Reg. 121
Reg. 122
MSB
LSB
7
Reserved
Registers 120–122 (0x078–0x07A) S/P DIF Channel Buffer Read Address
[19:0]
Register 124 (0x07C)
7
These registers contain the current address of the S/P DIF (IEC958)
read pointer in the Audio ES channel buffer. The LSB should be read first
since this captures the next significant byte and MSB in Registers 121
and 122. These should then be read immediately to ensure that the
correct captured value is read. When set, the most significant bit (bit 3
of Register 122) indicates that the read pointer has wrapped around from
the end address to the start address of the buffer.
Register 123 (0x07B) Reserved
MPEG Audio Extension Stream ID [4:0]
Reserved
Registers 125–127 (0x07D–0x07F)
Register Descriptions
Reserved
5
S/P DIF Channel Buffer Read Address [15:8]
S/P DIF Channel Buffer Read Address [7:0]
This register can be used by the host to program the
extension stream ID for multichannel MPEG audio
bitstreams. This register is used only if Register 143, bits
5-7
multichannel audio stream select enable. The Audio
Decoder provides only an S/P DIF (IEC958) formatted
output for multichannel MPEG audio bitstreams.
(page
4
4
4-34), are set to mode 0b101, MPEG
Read Only
Read Only
MPEG Audio Extension Stream ID [4:0]
S/P DIF Channel Buffer Read Address [19:16]
3
Reserved
Read Only
W [4:0]
0
0
[7:0]
[7:5]
[7:0]