L64105 LSI Logic Corporation, L64105 Datasheet - Page 108

• Manufacturer Part Number: L64105
• Description: Mpeg-2 Audio/video Decoder
• Manufacturer: LSI Logic Corporation

Figure 4.31
Figure 4.32
4-26
Reg. 100
Reg. 101
Reg. 96
Reg. 97
Reg. 98
Reg. 99
MSB
MSB
LSB
LSB
Registers 96–98 (0x060–0x062) Video ES Channel Buffer Write Address
[19:0]
Registers 99–101 (0x063–0x065) Audio ES Channel Buffer Write Address
[19:0]
7
7
These registers contain the current write pointer address of the Video ES
channel buffer. The LSB should be read first. since this captures the next
significant byte and MSB in Registers 97 and 98. These should then be
read immediately to ensure that the correct captured value is read. When
set, the most significant bit (bit 3 of Register 98) indicates that the write
pointer has wrapped around from the end address to the start address
of the buffer.
These registers contain the current write pointer address of the Audio ES
channel buffer. The LSB should be read first. since this captures the next
significant byte and MSB in Registers 100 and 101. These should then
be read immediately to ensure that the correct captured value is read.
When set, the most significant bit (bit 3 of Register 101) indicates that
the write pointer has wrapped around from the end address to the start
address of the buffer.
Register Descriptions
Reserved
Reserved
Video ES Channel Buffer Write Address [15:8]
Audio ES Channel Buffer Write Address [15:8]
Video ES Channel Buffer Write Address [7:0]
Audio ES Channel Buffer Write Address [7:0]
4
4
Read Only
Read Only
Read Only
Read Only
Video ES Channel Buffer Write Address [19:16]
Audio ES Channel Buffer Write Address [19:16]
3
3
Read Only
Read Only
1
0