L64105 LSI Logic Corporation, L64105 Datasheet - Page 335

• Manufacturer Part Number: L64105
• Description: Mpeg-2 Audio/video Decoder
• Manufacturer: LSI Logic Corporation

Table 10.1
Bits [2:0] DAC Output
0b000
0b001
0b010
0b011
0b100
0b101
0b110
0b111
Mode
MPEG decoder
Reserved
MPEG Decoder
Reserved
Linear PCM Decoder
Linear PCM Decoder output decimated
through on-chip filter to convert from
96-kHz to 48-kHz sample rate. This mode
should be selected if the output desired is
through a DAC that supports a 48-kHz
sample frequency only.
CD bypass
PCM FIFO
Audio Decoder Modes
When the host starts the selected audio decoder, audio frames/packets
are retrieved from the Audio ES Channel Buffer in SDRAM and decoded
and formatted. The three decoders parse most of the parameters from
the bitstream and store them in registers in the Host Interface. The host
reads these registers and writes decoder commands to other registers to
modify the audio.
The MPEG Decoder reproduces 16-bit audio samples from the bitstream
with 24-bit internal processing precision. The packetized Linear PCM
samples can be 16, 20, or 24 bits in length. The host can override the
bitstream sample resolution for all of the decoders by setting the
Overwrite Quantization bit in Register 366
the Host Quantization bits in the same register for 16, 20, or 24-bit
samples. The decoders truncate or extend the samples accordingly.
Audio Decoder Overview
S/P DIF (IEC958) Output
MPEG decoder output PCM samples con-
verted to IEC958 format
MPEG Formatter
Linear PCM Decoder
NOTE: If the sample frequency in the Linear
PCM bitstream is 96 kHz, then the IEC958
output is derived from an on-chip filter that
converts from 96-kHz to 48-kHz sample
frequency.
Same as DAC, converted to IEC958 format.
S/P DIF bypass
PCM FIFO
(page
4-89) and programming
10-3