L64105 LSI Logic Corporation, L64105 Datasheet - Page 299

• Manufacturer Part Number: L64105
• Description: Mpeg-2 Audio/video Decoder
• Manufacturer: LSI Logic Corporation

Therefore, the host must also program the required number of Main
Reads per Line from the frame store in Register 278
(page
4-65). This
value is the number of frame store pixels to be read divided by eight
since there are eight luma bytes in an SDRAM burst. For example, if the
source image is SIF resolution (352 pixels in width) and the target image
is full resolution (720 pixels in width), the required main reads per line is
equal to 352/8 = 44.
9.3.1 Vertical Timing
The active display area is bounded by the horizontal and vertical blanking
intervals. The blanking intervals for the Display Controller are defined by
the ITU-R BT.656 SAV/EAV timing codes. (Start of Active Video/End of
Active Video). These codes include three signals for timing; a vertical
blanking (V), a horizontal blanking (H), and an odd/even field (F). The
Display Controller can optionally output the ITU-R BT.656 SAV/EAV
timing codes on the pixel data bus by setting the ITU-R BT.656 Mode bit
in Register 284
(page
4-67). Regardless of the setting of the ITU-R
BT.656 Mode bit, the SAV/EAV control parameters must be programmed
for predictable operation of the L64105. In addition to providing the
SAV/EAV output codes and defining the active display area, these
parameters are also used for generating the Display Controller interrupts.
The ITU-R BT.656 control parameters are programmed in
Registers 303–305
(page
4-70). The horizontal position of the SAV/EAV
codes as an offset from the horizontal sync is programmable through the
SAV Start Column and the EAV Start Column Registers (306–308,
page
4-72).
Figure 9.3
shows the vertical timing for an NTSC system and
Figure 9.4
shows the timing for a PAL system.
Display Areas
9-7