L64105 LSI Logic Corporation, L64105 Datasheet - Page 129

• Manufacturer Part Number: L64105
• Description: Mpeg-2 Audio/video Decoder
• Manufacturer: LSI Logic Corporation

Figure 4.66
Figure 4.67
Figure 4.68
Figure 4.69
Reg. 222
Reg. 223
MSB
LSB
7
7
7
Register 219 (0x0DB) DMA SDRAM Read Data [7:0]
Register 220 (0x0DC) DMA SDRAM Write Data [7:0]
Register 221 (0x0DD)
Registers 222 and 223 (0x0DE and 0x0DF) VCO Test Low Freq [15:8]
7
Reserved
Address should be updated by the host only when the DMA read FIFO
is full, allowing a clean flush of the read FIFO. When updating the DMA
SDRAM Source Address, it should be written in MSB to LSB order. This
triggers the refill of the read FIFO at the new address.
During DMA read, the next byte from SDRAM to be read by the external
DMA is placed in this register.
During DMA write, the external DMA writes the next byte to be written to
SDRAM in this register.
Register 221 holds the results of the PLL test. See also Registers 204
bit 0
See Registers 204, bit 0
Memory Interface Registers
(page
DMA SDRAM Read Data (DMA only) [7:0]
DMA SDRAM Write Data (DMA only) [7:0]
4-43), 207-212
4
VCO Test Low Freq [15:8]
VCO Test Low Freq [7:0]
Read Only
(page
W
Read Only
Frequency
Test Pass
(page
PLL VCO
Low
R/W
R/W
3
4-43), and 207-212
4-45), and 222-223.
Read Only
Frequency
PLL VCO
Test Pass
High
2
Detect Low
PLL Phase
Read Only
Frequency
Test Pass
(page
1
4-45).
Detect High
PLL Phase
Read Only
Frequency
Test Pass
0
0
0
0
4-47