L64105 LSI Logic Corporation, L64105 Datasheet - Page 163

• Manufacturer Part Number: L64105
• Description: Mpeg-2 Audio/video Decoder
• Manufacturer: LSI Logic Corporation

Figure 4.121 Register 357 (0x165)
Table 4.3
Select
Bits
0b000
0b001
0b010
0b011
0b100
0b101
0b110
0b111
7
DAC Interface
MPEG Decoder
Reserved
MPEG Decoder
Reserved
PCM Decoder
PCM Decoder output decimated through
on-chip filter to convert from 96-kHz to
48-kHz sample rate. This mode should
only be set if the output is for a DAC that
supports 48-kHz sample frequency only.
CD Bypass
PCM FIFO
Audio Decoder Mode
Select [2:0]
Audio Decoder Modes
Reserved
Audio Decoder Mode Select [2:0]
Audio Decoder Registers
5
Clear these bits when writing to this register.
These bits control the selection of modes that are
allowable in the Audio Decoder according to
See the Important note following the description of the
Audio Formatter Start/Stop bit, bit 7 in Register 356.
4
S/P DIF Interface
MPEG Decoder output PCM samples converted
to IEC958 format
MPEG Formatter
Linear PCM samples converted to IEC958 format.
NOTE: If the sample frequency in the Linear PCM
bitstream is 96 kHz, then the IEC958 output is
derived from an on-chip filter that converts from
96-kHz to 48-kHz sample frequency.
Same as DAC, converted to IEC958 format.
S/P DIF bypass
PCM FIFO
Reserved
Table
R/W [7:5]
0
4.3.
[4:0]
4-81