L64105 LSI Logic Corporation, L64105 Datasheet - Page 282

• Manufacturer Part Number: L64105
• Description: Mpeg-2 Audio/video Decoder
• Manufacturer: LSI Logic Corporation

8.5.3 Channel Buffer Underflow Panic Repeat
8.5.4 Rip Forward Mode
8-40
When this feature is enabled and the decoder detects that the Video ES
Channel Buffer is in danger of underflowing, it automatically freezes the
display on the last field of the currently displaying picture. The freeze is
automatically removed when the channel buffer has filled to an adequate
level. During the panic condition, the decoder pauses; it does not request
any bytes from the channel for decoding.
To enable this feature, the host sets the Video Numitems/Pics Panic
Mode Select bits in Register 69
number of items (64-bit words) or 0b10 to select number of pictures. The
host must then enter an item or picture threshold value in Registers 134
through 136
number of items or pictures in the Video ES Channel Buffer with the
programmed threshold value. If the actual number falls below the
threshold, a “panic” signal is sent to the Video Decoder. The Video
Decoder responds by repeating a frame to let the Video ES Channel
Buffer refill above the threshold. The panic signal is sampled by the
decoder just before reconstruction of the picture is about to begin. Note
that the decoder pauses for the panic signal to clear even if the host has
commanded the decoder to skip a frame.
Setting the Rip Forward Mode Enable bit in Register 238
enables the Rip Forward Mode. In this mode, the decoder processes
pictures as fast as it can without regard to the status of the display, i.e.,
the rate control for the decode with respect to the Vertical Sync of the
display is turned off. The rate control for the decode is governed by the
Rip Forward Display Single Step Command bit in Register 238
(page
it receives both a picture start code and the first slice start code, and has
processed the picture header. The decode for that picture only proceeds
when the single step bit is set. The single step bit is cleared on reading
by the decoder.
Video Decoder Module
Note:
4-53). The on-chip microcontroller monitors the single step bit after
(page
This operation can violate the correct Video Buffering
Verifier (VBV) model operation and is generally used in trick
modes when the VBV is invalid.
4-32). The Channel Buffer Controller compares the
(page
4-22) to either 0b01 to select
(page
4-52)