L64105 LSI Logic Corporation, L64105 Datasheet - Page 187

• Manufacturer Part Number: L64105
• Description: Mpeg-2 Audio/video Decoder
• Manufacturer: LSI Logic Corporation

transfer the 8-byte data block through the registers in big or little endian
order by setting or clearing the Host SDRAM Transfer Byte Ordering bit
in Register 193
(page
4-39). The L64105 operates in big endian mode,
i.e., byte 0 occupies the upper bits of the word and byte 8 occupies the
lower bits.
The transfers are paced by the FIFO status bits in Register 192
(page
4-38). The host must read the status bits before writing or reading
the next 8 bytes to or from the data registers and before starting a new
transfer.
5.4.1.1 Host Read
The host read operation uses the SDRAM Source Address (Registers
199 through 201) as the SDRAM pointer for reading. This address is
auto-incremented after a word is loaded from SDRAM into the on-chip
FIFO.
Figure 5.8
shows the flow for host reads from and writes to SDRAM. The
host begins an SDRAM read operation by setting or clearing the Host
SDRAM Byte Ordering bit (if necessary) to change the endian mode and
then writing the Host SDRAM Source Address. Typically, the Host
SDRAM Byte Ordering bit is set or cleared by the host at initialization
and not changed again. When the host writes in the LSB of the source
address, the L64105 automatically resets the pointers of the host read
FIFO
(Figure
5.1) and begins to fill the FIFO with new data from the
source address.
After setting the source address, the host must check the Host Read
FIFO Empty status bit. If the host read FIFO is not empty, the host may
read 1 byte from the Host SDRAM Read Data register. The host may
continue to read from this register until 8 bytes have been read from the
host read FIFO. After 8 bytes are read, the FIFO read pointer is
automatically incremented and the host can continue to read data.
When the host is finished with the current host SDRAM read operation,
it must wait for the Host Read FIFO Full bit to be set before beginning
any new SDRAM operation (host r/w, DMA r/w, or block move.)
SDRAM Access
5-11