L64105 LSI Logic Corporation, L64105 Datasheet - Page 145

• Manufacturer Part Number: L64105
• Description: Mpeg-2 Audio/video Decoder
• Manufacturer: LSI Logic Corporation

Figure 4.93
Field Sync
Enable
7
Register 276 (0x114)
6
Odd/Not Even Field
Top/Not Bottom Field
Last Field
Horizontal Filter Enable
Horizontal Filter Select
Display Mode [3:0]
Video Interface Registers
Display Mode [3:0]
The display controller sets this bit at the first horizontal
sync after a vertical sync during an odd field. This bit is
cleared at the first horizontal sync after a vertical sync
during an even field.
This bit is set at the first horizontal sync after a vertical
sync when top-field data is being displayed. This bit is
cleared at the first horizontal sync after a vertical sync
when bottom-field data is being displayed.
When set, this bit indicates that the current field being
displayed is the last field in the frame.
Setting this bit enables the horizontal interpolation filter.
This bit sets the frequency response of the output filter to
one of two preprogrammed values. When this bit is 1,
frequency response ‘A’ is selected; when the bit is 0,
frequency response ‘B’ is selected. See
“Horizontal Postprocessing Filters,”
The host should encode these bits based on the
characteristics of the source video as shown in
These bits cause the display controller to operate in one
of 12 different postprocessing modes. Refer to
9.6, “Display Modes and Vertical Filtering,”
descriptions of each of these modes.
3
Filter Select
Horizontal
2
Filter Enable
for more details.
Horizontal
1
Section 9.8,
for
Table
R/W [6:3]
Last Field
Section
R/W 1
R/W 2
0
4.1.
4-63
R 6
R 7
R 0