L64105 LSI Logic Corporation, L64105 Datasheet - Page 174

• Manufacturer Part Number: L64105
• Description: Mpeg-2 Audio/video Decoder
• Manufacturer: LSI Logic Corporation

4-92
Report End of Test
Initiate Memory Test
Data Pattern to be Applied to RAM [1:0]
Memory Test Output Select
Reserved
Register Descriptions
Note:
Operational
Mode [1:0]
0b00
0b01
0b10
0b11
This bit is cleared by the L64105 at the conclusion of the
memory test.
The host sets this bit to start the memory test specified
by bits 0 and 1 of this register.
This field contains the 2-bit repeated pattern to be
applied during the automated RAM test. These bits are
set by the L64105 during automated RAM test and
should be set by the host during host-controlled testing of
RAM (mode 0b01 of the memory test).
Setting this bit enables the overall memory test pass/fail
status to assert the AREQn output signal of the L64105
for test pass.
This bit should be set only when a memory test is to be
run. This bit defaults to 0 at reset and should be main-
tained at 0 during normal functional mode.
Clear these bits when writing to this register.
Description
Normal (no test)
Host-controlled testing of memories
Automated RAM test
Automated ROM test
for a single address
W [4:3]
R/W 5
[7:6]
W 2
R 2