L64105 LSI Logic Corporation, L64105 Datasheet - Page 106

• Manufacturer Part Number: L64105
• Description: Mpeg-2 Audio/video Decoder
• Manufacturer: LSI Logic Corporation

Figure 4.26
Figure 4.27
Figure 4.28
4-24
Reg. 78
Reg. 79
Reg. 80
Reg. 81
Reg. 82
Reg. 83
MSB
MSB
MSB
LSB
LSB
LSB
Registers 78 and 79 (0x04E and 0x04F) Audio ES Channel Buffer End
Address [13:0]
Registers 80 and 81 (0x050 and 0x051) Video PES Header Channel Buffer
Start Address [13:0]
Registers 82 and 83 (0x052 and 0x053) Video PES Header Channel Buffer
End Address [13:0]
7
7
7
Reserved
Reserved
Reserved
These registers allow the host to program the Audio ES channel buffer
end address. The address is entered as if it were the upper 14 bits of a
21-bit address for a conventional 2M x 16 RAM address. The Memory
Interface of the L64105 converts the address to an SDRAM address at
a 256-byte boundary in SDRAM. This register should only be updated
while the channel is stopped (reset).
These registers allow the host to program the Video PES Header
channel buffer start address. The address is entered as if it were the
upper 14 bits of a 21-bit address for a conventional 2M x 16 RAM
address. The Memory Interface of the L64105 converts the address to
an SDRAM address at a 256-byte boundary in SDRAM. This register
should only be updated while the channel is stopped (reset).
These registers allow the host to program the Video PES Header
channel buffer end address. The address is entered as if it were the
upper 14 bits of a 21-bit address for a conventional 2M x 16 RAM
Register Descriptions
6
6
6
Video PES Header Channel Buffer Start Address [7:0]
Video PES Header Channel Buffer End Address [7:0]
Audio ES Channel Buffer End Address [7:0]
5
5
5
Video PES Header Channel Buffer Start Address [13:8]
Video PES Header Channel Buffer End Address [13:8]
Audio ES Channel Buffer End Address [13:8]
R/W
R/W
R/W
R/W
R/W
R/W
0
0
0