L64105 LSI Logic Corporation, L64105 Datasheet - Page 36

• Manufacturer Part Number: L64105
• Description: Mpeg-2 Audio/video Decoder
• Manufacturer: LSI Logic Corporation

2-6
CH_DATA[7:0] Channel Data Bus
AVALIDn
VVALIDn
ERRORn
DCK
I/O Signal Descriptions
The CH_DATA bus is used to transfer 8-bit, parallel
bitstreams into the L64105. The maximum transfer rate
over this interface is 20 Mbps in worst case conditions.
The peak data rate may increase above this rate
depending on system SDRAM usage.
Audio Data Valid
The channel device asserts this signal in response to
AREQn when the data byte it placed on the CH_DATA
bus is valid. The L64105 transfers the byte in when
AVALIDn is deasserted. This signal can be used with the
DCK input for synchronous transfers.
Video Data Valid
The channel device asserts this signal in response to
VREQn when the data byte it placed on the CH_DATA
bus is valid. The L64105 transfers the byte in when
VREQn is deasserted. This signal can be used with the
DCK input for synchronous transfers. This signal is used
only in the A/V PES stream mode when the channel input
is a program from a transport stream demultiplexer. Use
the AVALIDn signal for all data bytes in program stream
modes.
Bitstream Error
ERRORn is asserted by the channel device to signal
uncorrectable errors in the bitstream and is used by the
L64105 to invoke error handling routines. It is latched by
the L64105 on the rising edge of AVALIDn or VVALIDn.
Channel Clock
The DCK is a free-running clock from the external
channel device. It must have a period
SYSCLK (27 MHz). DCK, together with the AVALIDn and
VVALIDn signals, is used to write data synchronously to
the L64105 channel input.
3 x that of
Input
Input
Input
Input
Input