L64105 LSI Logic Corporation, L64105 Datasheet - Page 126

• Manufacturer Part Number: L64105
• Description: Mpeg-2 Audio/video Decoder
• Manufacturer: LSI Logic Corporation

Figure 4.61
4-44
7
Reserved
Register 205 (0x0CD)
6
Control for Programmable Delay Path 2 [1:0]
Phase Locked Status
Internal Lock Counter State [1:0]
Register Descriptions
5
Internal SDRAM State [2:0]
Note that the delays are in units of del05, a delay of
0.5 ns at nominal conditions (nominal process factor,
25 ˚C, and V
This register controls the selection of delay cells on the
incoming 81-MHz clock in scan test mode or bypass
mode. This register is only used in diagnostic mode and
during manufacturing test.
Control Bits
0b00
0b01
0b10
0b11
Note that the delays are in units of del1, a delay of 1.0 ns
at nominal conditions (nominal process factor, 25 ˚C, and
V
When this bit is set, the two internal clocks (81 MHz and
27 MHz) are synchronized.
Used to monitor synchronization of the 81-MHz and
27-MHz clocks (diagnostics only).
Bits [2:1]
0b00
0b01
0b10
0b11
DD
= + 3.3 V).
DD
Description
none
del1 x 1
del1 x 2
del1 x 3
3
Description
No sync yet
Got sync for 1 cycle
Got sync for 2 cycles
Got sync for at least 3 cycles
= + 3.3 V).
Internal Lock Counter State
2
[1:0]
1
Phase Locked
R/W [7:6]
Status
R [2:1]
0
R 0