L64105 LSI Logic Corporation, L64105 Datasheet - Page 359

• Manufacturer Part Number: L64105
• Description: Mpeg-2 Audio/video Decoder
• Manufacturer: LSI Logic Corporation

10.8 DAC Interface
Figure 10.10 DAC Output Mode: PCM Sample Precision = 16 Bit
(Invert LRCLK=0)
(Invert LRCLK=1)
ASDATA
LRCLK
LRCLK
BCLK
Note: S means sign-extension (0 for positive PCM values, 1 for negative PCM values).
Right PCM
Right PCM
R1
N-1
N-1
R0
The DAC Interface in the Audio Decoder converts the 16-, 20-, or 24-bit
parallel PCM data received from the decoders into 32-bit, serial frames
and transmits them to the external DAC. A demultiplexer controlled by the
Audio Decoder Mode Select bits in Register 357
output of one of the three decoders or the PCM FIFO as the DAC
Interface input.
The audio samples are multiplied by a scale factor, PCM Scale, in the
DAC Interface to control the output volume. At reset and power on, the
PCM Scale [7:0] bits in Register 362 are set to 0xFF to pass the input
samples through the interface with no change in level. The host can write
to the register to scale the samples level down in increments of 1/256.
Setting the PCM Scale bits to 0x00 mutes the audio output. The output
samples are sign-extended to 32 bits as shown in
Figure
DAC Interface
(Sixteen sign extension bits)
S
S
10.12.
S L15
Left PCM
Left PCM
N-1
N
L14
L1
L0
(Sixteen sign extension bits)
S
S
S R15 R14
Right PCM
Right PCM
N
N
(page
Figure 10.10
4-81) selects the
R1
R0
through
Left PCM
S
Left PCM
N+1
10-27
N
S