L64105 LSI Logic Corporation, L64105 Datasheet - Page 230

• Manufacturer Part Number: L64105
• Description: Mpeg-2 Audio/video Decoder
• Manufacturer: LSI Logic Corporation

Figure 7.1
7.2 SDRAM Configurations
7-2
SYSCLK (27 MHz)
L64105 Decoder
DCK ( 9 MHz)
CH_DATA[7:0]
Interface
Host
Memory Interface Block Diagram
19-bit Address Bus
The Memory Interface contains Byte Enable Logic and an Address
Converter. The Byte Enable Logic converts the internal 8-byte words to
2-byte SDRAM words and vice versa. The Address Converter converts
the 19-bit internal addresses to chip selects SCSn and SCS1n, and
multiplexed, 12-bit, row/column addresses. All transfers are in minimum
bursts of four SDRAM words. Once a read or write cycle is initiated,
however, the Address Converter continually increments the SDRAM
address until the host or internal microcontroller terminates the transfer.
The SDRAM interface uses commodity SDRAMs in the following
configurations:
Memory Interface
Interface
Channel
64-bit Data Bus
512 x 16-bit page size
81-MHz SDRAM clock (162 Mbytes/s max.)
PLL
81 MHz Clock
Microcontroller
Converter
Interface
Memory
Address
Enable
Logic
Byte
SCSn
SBD[15:0]
SBA[11:0]
SCASn
SRASn
SCS1n
(Optional)
1 M x 16
1 M x 16
SDRAM
SDRAM