L64105 LSI Logic Corporation, L64105 Datasheet - Page 231

• Manufacturer Part Number: L64105
• Description: Mpeg-2 Audio/video Decoder
• Manufacturer: LSI Logic Corporation

7.3 SDRAM Timing and Modes
Typical SDRAM devices are the Samsung KM416S1120A or NEC
The SDRAM interface uses a CAS latency of 3 and a burst length of 4.
The 4-word burst provides high bandwidth transfer from the SDRAM
16-bit bus to the internal 64-bit bus. The mode register in the SDRAM is
programmed to have CAS Latency = 3, and Burst Length = 4.
For systems with 16 Mbit of external SDRAM, the SCSn signal of the
L64105 is used as the only chip select (CS). The SCS1n signal is left
unconnected. For systems with 32 Mbit of SDRAM, the SCSn signal is
the chip select for the lower-address SDRAM and the SCS1n signal is
the chip select for the higher-address SDRAM since they share the same
data bus. Note that both SDRAM devices must have a 512 x 16 bit page
size to match the interface’s column and row addressing.
The timing of the SDRAM is very critical and requires careful layout of
the PC board traces between the L64105 and the SDRAM device. The
SDRAM power and ground lines must be noise-free with sufficient
bypass capacitors. The traces connecting the SDRAM to the L64105
must be short and direct. The pinout on the L64105 has been optimized
for a clean, single-layer layout to standard, TSOP (II), 50-pin SDRAM
packages. The L64105 PLLVDD and PLLVSS pins supply power to the
on-chip PLL which generates the 81-MHz clock. These pins must be
isolated from the digital power and ground pins and have sufficient
bypass coupling near the L64105 to ensure a noise-free PLL power and
ground connection.
show typical timing seen for standard SDRAMs during read, write, and
SDRAM Timing and Modes
PD4516161.
Page Break Penalty = 6 to 7 cycles (81 MHz)
Memory capacity: 16 or 32 Mbit using one or two 1M x 16 bit chips
Table
7.1,
Figure
7.2,
Figure
7.3, and
Figure 7.4
7-3