L64105 LSI Logic Corporation, L64105 Datasheet - Page 181

• Manufacturer Part Number: L64105
• Description: Mpeg-2 Audio/video Decoder
• Manufacturer: LSI Logic Corporation

Figure 5.4
Figure 5.5
5.3 Register Access and Functions
5.3.1 General Functions
(On DSn pin)
(On DSn pin)
DTACKn
DTACKn
WRITEn
READn
D[7:0]
A[8:0]
D[7:0]
A[8:0]
CSn
CSn
Intel Mode Write Timing
Intel Mode Read Timing
The registers of the L64105 Decoder are accessed when the host places
their address (0x000 through 0x1FF) on the A[8:0] input lines of the chip
and starts a read or write operation.
The registers contain status bits and fields, control bits and fields,
SDRAM buffer pointers for bitstream header fields and data, System
Clock Reference (SCR) capture and compare values and control bits,
and host to SDRAM access addresses and data. The latter group are
described in the following section. A complete summary of all of the
registers is included in
bits and fields are provided in
Register Access and Functions
Chapter 3
Chapter
and detailed descriptions of all register
4.
5-5