L64105 LSI Logic Corporation, L64105 Datasheet - Page 229

• Manufacturer Part Number: L64105
• Description: Mpeg-2 Audio/video Decoder
• Manufacturer: LSI Logic Corporation

7.1 Overview
Chapter 7
Memory Interface
This chapter describes the memory interface block of the L64105
Decoder. It contains the following sections:
The L64105 MPEG-2 Audio/Video Decoder has a dedicated memory
interface which is used for buffering the input channel data stream, video
frame storage during decode and display, and storing OSD graphics
information. The interface includes a 16-bit data bus and a 12-bit
multiplexed row/column address bus operating at 81 MHz to commodity
SDRAMs. The L64105 SDRAM interface uses an on-chip Phase-Locked
Loop (PLL) to generate the 81-MHz clocking signal from the 27-MHz
system clock. Since the L64105 has a 64-bit wide internal bus, all
SDRAM operations are bursts of four 16-bit accesses. All internal
addressing and internal references are relative to 64-bit SDRAM bursts.
The block diagram for the Memory Interface is shown in
interfaces the internal address and 64-bit data bus of the L64105 to the
12-bit address bus and 16-bit data bus of the SDRAM(s). Addresses on
the internal bus of the L64105 are in the form of simple RAM addresses
for 2M x 16-bit RAM. Since the SDRAM is set up for a four-word burst
at each access, the internal address bus of the L64105 is only 19 bits
wide.
Section 7.1, “Overview,” page 7-1
Section 7.2, “SDRAM Configurations,” page 7-2
Section 7.3, “SDRAM Timing and Modes,” page 7-3
Section 7.4, “SDRAM Refresh and Arbitration,” page 7-5
Section 7.5, “Memory Channel Buffer Allocation,” page 7-6
Section 7.6, “Memory Frame Store Allocation,” page 7-9
Section 7.7, “Summary,” page 7-12
Figure
7.1. It
7-1