L64105 LSI Logic Corporation, L64105 Datasheet - Page 189

• Manufacturer Part Number: L64105
• Description: Mpeg-2 Audio/video Decoder
• Manufacturer: LSI Logic Corporation

Figure 5.8
SDRAM Access
Yes
No
No
Write SDRAM Source Address
201[0:2] = [18:16]
200 = [15:8]
199 = [7:0]
(LSB must be set last)
Pause One Clock Cycle
Read 1-8 bytes from
Read
FIFO Empty?
192[0] = 1?
192[1] = 1?
Host Read
Host Read
FIFO Full?
Host Read/Write Flowchart
No
Transfer
Done?
194
Yes
Yes
Set Host Endian Mode (if needed)
193[3] = Host Endian
Begin
End
Write SDRAM Target Address
Pause One Clock Cycle
198[0:2] = [18:16]
197 = [15:8]
196 = [7:0]
(LSB must be set last)
Write 8 bytes to
FIFO Empty?
192[3] = 1?
192[2] = 1?
FIFO Full?
Host Write
Yes
Host Write
Yes
Transfer
Done?
195
Write
No
Yes
No
No
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