L64105 LSI Logic Corporation, L64105 Datasheet - Page 154

• Manufacturer Part Number: L64105
• Description: Mpeg-2 Audio/video Decoder
• Manufacturer: LSI Logic Corporation

Figure 4.110 Registers 306–308 (0x132–0x134) SAV/EAV Start Columns [10:0]
Figure 4.111 Register 309 (0x135)
4.6 Audio Decoder Registers
Figure 4.112 Register 336 (0x150)
4-72
MPEG - ID
Reg. 306
Reg. 307
Reg. 308
MSBs
LSB
LSB
7
7
Reserved
MPEG - layer_code [1:0]
7
6
The host can write to these registers to define the start of SAV and EAV
in terms of the number of system clocks from the horizontal sync. Clear
bits 7 and 3 in Register 308 when writing to it.
Display Start Command
Reserved
Registers 310–335 (0x136–0x14F)
MPEG - bitrate_index [3:0]
Register Descriptions
6
EAV Start Column [10:8]
5
R/W
protection_bit
Setting this bit causes the display unit to start operation.
Clear these bits when writing to this register.
MPEG mode bitrate_index parsed from the bitstream.
Table 4.2
0x0 code indicates any fixed bitrate not included in the
table where fixed means that a frame contains either N
or N+1 slots, depending on the value of the padding bit.
Reserved
MPEG -
4
SAV Start Column [7:0]
EAV Start Column [7:0]
shows the decoding of the index by layer. The
4
R/W
R/W
3
Reserved
3
Reserved
MPEG - bitrate_index [3:0]
2
SAV Start Column [10:8]
1
R/W
Display Start
Command
R [3:0]
R/W 0
0
0
0
[7:1]
[7:0]