L64105 LSI Logic Corporation, L64105 Datasheet - Page 440

• Manufacturer Part Number: L64105
• Description: Mpeg-2 Audio/video Decoder
• Manufacturer: LSI Logic Corporation

PREQn signal
Presentation Time Stamp
presentation units synchronized
priority interrupts 4-11,
private_2 stream packet data errors
processing rate 4-52,
program counter
program streams
programmable background Y/Cb/Cr bits
programmable delay
programs
progressive frame (defined)
PS
PSI
psychoacoustic modeling
PTS
pulldown control 8-41, 9-38,
pulldown operation timing
PXD
Q
Q table
quality (images)
quant matrix extension 8-13,
quantization intervals
quantization level
quantization values
quantizer scale
R
RAM
RAM test registers
range control 4-87,
raster mapper
rate control (automatic) 8-43,
rate matching
IX-24
description
timing
usage overview
error handling
preparsing 6-9,
system channel buffer map
address bits
entry availability
ready bit
linear PCM streams
MPEG samples 10-3,
PCM samples
changes
operational mode
output select
status
B-7
B-7
B-7
B-7
B-7
8-14
11-17
4-93
6-1
A-6
4-56
1-5
2-5
9-22
2-5
A-6
4-56
9-16
4-92
4-57
6-1
6-21
A-4
10-16
6-18
4-91
10-26
10-17
4-88
4-57
4-43
4-91
A-3
4-55
to
5-10
10-15
Index
10-12
A-8
6-24
A-10
9-39
9-16
9-39
8-14
8-44
6-19
4-3
6-22
4-60
RDYn signal
read pointers
READ signal
read/write strobe
READn signal
reads
description
audio DTS compare
audio ES channel buffer end address
audio ES channel reset
audio sync code address
auxiliary data
buffer start
comparison enables
current address
elementary stream mode
external SDRAM
picture start code
S/P DIF buffer reset
transport streams
user data
video DTS compare
video ES channel reset
description
description
A/V data
audio items remaining
Aux data FIFO port
Aux data layer
decimation filter and
DMA controller 5-15,
FIFO
FIFO status
frame stores 9-6,
host 2-3,
host flowchart
Intel mode timing
Motorola mode timing
number of pictures in video ES buffer
OSD palette
Q table 4-56, 4-57,
ready interrupt
scan line display
SCR counter
SDRAM 4-47,
SDRAM timing cycle
SDRAM timing diagram
audio ES channel buffer
video ES channel buffer
starting addresses
diagram
diagram
starting addresses
1-3
6-8
4-41
2-4
8-24
2-4
1-3
2-4
2-4
6-28
2-4
2-4
11-13
11-11
4-38
4-60
5-7
8-21
2-4
5-13
5-10
4-18
4-2
4-4
6-27
4-65
9-30
5-5
4-31
6-25
8-14
to 5-13, 7-2,
4-19
4-28
4-29
4-21
4-20
9-20
7-4
5-17
4-46
5-4
4-42
4-33
4-20
4-20
11-7
6-14
4-31
4-27
4-28
9-2
10-7
4-38