L64105 LSI Logic Corporation, L64105 Datasheet - Page 177

• Manufacturer Part Number: L64105
• Description: Mpeg-2 Audio/video Decoder
• Manufacturer: LSI Logic Corporation

5.1 Overview
Chapter 5
Host Interface
This chapter describes the host’s interface to the L64105 chip and
external SDRAM. Refer to
interface between the L64105 and external SDRAM. This chapter
includes the following sections:
Figure 5.1
communicates with the L64105 and external SDRAM through 512, 8-bit
registers. (All of the registers are not currently used; some are reserved
for future changes to the chip.) The chip provides a 9-bit input address
bus, A[8:0], to reach all 512 registers and a register-wide (8-bit),
bidirectional data bus, D[7:0]. Refer to
registers and
The host accesses external SDRAM through a set of registers, byte
enabling logic for big/little endian control, read and write FIFOs, and the
Memory Interface block of the L64105 chip.
Section 5.1, “Overview,” page 5-1
Section 5.2, “Interface Signals,” page 5-2
Section 5.3, “Register Access and Functions,” page 5-5
Section 5.4, “SDRAM Access,” page 5-10
shows a block diagram of the Host Interface. The host
Chapter 4
for descriptions of the registers.
Chapter 7
for a complete description of the
Chapter 3
for a summary of the
5-1