L64105 LSI Logic Corporation, L64105 Datasheet - Page 40

• Manufacturer Part Number: L64105
• Description: Mpeg-2 Audio/video Decoder
• Manufacturer: LSI Logic Corporation

2-10
BCLK
LRCLK
A_ACLK
AUDIO_SYNCn
ACLK_32, ACLK_441, ACLK_48
I/O Signal Descriptions
DAC Bit Clock
Serial data bit clock used by the L64105’s DAC Interface
to serialize the decoded audio data and by the external
DAC to clock it in on the rising edge. BCLK is derived
from one of the ACLK_ inputs under host control in
normal modes and is the CD_BCLK input in CD Bypass
mode.
DAC Left/Right Sample Clock
Used to indicate which samples belong to the left and
right stereo channels. In default mode, LRCLK is
asserted when the right channel sample is on the
ASDATA pin and deasserted when the left channel
sample is on the ASDATA pin. The host can set the Invert
LRCLK bit in Register 363 (page 4-84) to invert the sense
of the clock (HIGH for left channel, LOW for right).
DAC Clock
This clock is buffered from the selected input ACLK_ (see
the following ACLK_ description). In CD-bypass mode,
this clock comes directly from the CD_ACLK input pin.
Audio Sync Strobe
Provides an indication of Audio Decoder synchronization
to the bitstream. Used in transport systems requiring
hardware sync controls. This is an active LOW pulse at
the time of the audio frame decode start.
Audio Reference Clocks
Host selectable audio reference clocks from which clocks
for the external DAC, internal DAC Interface, and internal
S/P DIF Interface are derived.
ACLK_32 = 32 kHz * N,
ACLK_441 = 44.1 kHz * N, and
ACLK_48 = 48 kHz * N
where N = 768, 512, 384, or 256.
At least one of the three ACLK_ inputs must be supplied
and it must be integrally divisible into the required sample
rate clocks. See the ACLK Select bits in Register 363
(page 4-84) and the ACLK Divider Select bits in Register
364 (page 4-85).
Output
Output
Output
Output
Input