L64105 LSI Logic Corporation, L64105 Datasheet - Page 122

• Manufacturer Part Number: L64105
• Description: Mpeg-2 Audio/video Decoder
• Manufacturer: LSI Logic Corporation

4-40
Host SDRAM Transfer Byte Ordering
Refresh Extend [1:0]
Register Descriptions
transferred to the internal 8 x 64 write FIFO. Note that
separate counters and addresses are maintained for host
and DMA write operations. The on-chip SDRAM
controller continuously empties the write FIFO and
transfers the data to the specified SDRAM target
address. The target address is automatically incremented
for every 64-bit word transferred from the write FIFO to
the SDRAM.
During DMA Write Mode, DREQn is asserted only when
there is more space in the write FIFO for writing. It is the
responsibility of the external DMA controller to keep track
of the DMA transfer count. On receiving DMA done from
the external DMA controller, the external host should
always check for read FIFO full (for DMA read) or write
FIFO empty (for DMA write) before returning the DMA
Mode back to Idle.
Block Move: The host specifies the source address, the
target address and a block transfer count. The internal
SDRAM controller uses the read FIFO to continuously
load SDRAM data from the source address and empties
the contents of the read FIFO to the target address.
When the total number of transferred words reaches the
block transfer count, the SDRAM Transfer Done Interrupt
bit in Register 4
interrupt is not masked, and the DMA Mode is reset to
Idle, 0b00. Refer to
further detail.
During block moves, the DREQn signal is held high. DMA
and block moves may NOT occur simultaneously.
Little Endian/Big Endian
This bit must be set if the host operates in big endian
mode, i.e., with byte 0 in bits [63:56] and byte 7 in bits
[7:0]. Since the L64105 operates in big endian mode, no
byte swapping occurs at the host interface. If the host is
little endian, this bit must be cleared to enable byte
swapping.
These bits specify the multiplying factor for SDRAM
refreshes. The table below lists the number of refresh
(page
Section 5.4, “SDRAM Access,”
4-3) is set, INTRn is asserted if the
R/W [5:4]
R/W 3
for