L64105 LSI Logic Corporation, L64105 Datasheet - Page 14
L64105
Manufacturer Part Number
L64105
Description
Mpeg-2 Audio/video Decoder
Manufacturer
LSI Logic Corporation
Datasheet
1.L64105.pdf
(454 pages)
- Current page: 14 of 454
- Download datasheet (5Mb)
xiv
5.10
6.1
6.2
6.3
6.4
6.5
6.6
6.7
6.8
6.9
6.10
6.11
6.12
6.13
6.14
6.15
6.16
7.1
7.2
7.3
7.4
7.5
7.6
8.1
8.2
8.3
8.4
8.5
8.6
8.7
8.8
8.9
8.10
9.1
9.2
9.3
9.4
9.5
Contents
Block Move Flowchart
Channel Interface Block Diagram
Asynchronous Channel Interface Timing
xVALIDn Input Synchronization Circuits
Synchronous Valid Signals Timing
L64105 A/VREQn Circuits
Elementary Stream Buffering
PES Packet Structure
Preparsing an MPEG-1 System Stream
System PES Channel Buffer Map for MPEG-1 Streams
System Channel Buffer Map for Program Streams
Audio ES Channel Buffer Map for Linear PCM Audio
Audio ES Channel Buffer Map for MPEG Audio
Video ES Channel Buffer Map
Parsing an Audio/Video PES Transport Stream
MPEG-1/MPEG-2 Channel Interface Operation
A/V PES Mode Channel Interface Operation
Memory Interface Block Diagram
SDRAM Timing Requirements for Reads
SDRAM Timing Requirements for Writes
SDRAM Timing Requirements for Refresh
Luma Frame Store Organization
Chroma Frame Store Organization
Video Decoder Block Diagram
Time Line for Frame Picture
Time Line for Field Picture
Frame Store Organization in Normal Mode
Single Skip with and without Display Freeze
Frame Repeat Modes
Setting Up Rip Forward/Display Override Command
Automatic Rate Control
Using Force Rate Control in Rip Forward Mode
Example of Sequence End Processing
Video Interface Block Diagram
Display Areas Example
Vertical Timing Vcodes and Fcodes for NTSC
Vertical Timing Vcodes and Fcodes for PAL
Sync Input Timing
5-19
6-13
6-15
6-16
6-17
6-19
6-20
6-21
6-21
6-24
6-30
6-31
7-10
8-28
8-29
8-31
8-37
8-39
8-42
8-45
8-46
8-47
9-10
6-3
6-4
6-6
6-6
6-7
7-2
7-4
7-5
7-5
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8-3
9-3
9-6
9-8
9-9
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