L64105 LSI Logic Corporation, L64105 Datasheet - Page 41

• Manufacturer Part Number: L64105
• Description: Mpeg-2 Audio/video Decoder
• Manufacturer: LSI Logic Corporation

2.7 Miscellaneous and Test Interfaces
SPDIF_IN
SPDIF_OUT
PLLVDD
Figure 2.2
VDD
PLLVSS
RESETn
Miscellaneous and Test Interfaces
1 F
PLLVSS
Ferrite Bead
PLLVDD Decoupling Circuit
External S/P DIF
This input is directly connected to the SPDIF_OUT pin
when the host selects the S/P DIF Bypass mode.
S/P DIF Output
IEC958 formatted output of the L64105’s S/P DIF
Interface in normal modes and SPDIF_IN in S/P DIF
Bypass mode.
PLL Power Supply
This pin provides power (3.3 V) to the on-chip PLL for
deriving the 81-MHz SDRAM clock. This power supply
pin must be isolated from the digital power plane with the
filter shown in
voltage regulator.
PLL Ground
This pin provides ground to the on-chip PLL for deriving
the 81-MHz SDRAM clock. This supply pin must be
isolated from the digital ground plane, and only
connected at the voltage regulator. It should be
decoupled from the PLLVDD pin.
Reset
When RESETn is asserted, the L64105 resets its internal
microcontroller, FIFO controllers, state machines, and
registers. The minimum RESETn pulse width is 8 cycles
of SYSCLK (8/27 MHz = 300 ns). SYSCLK and the
selected ACLK (ACLK_32, ACLK_441, or ACLK_48)
must be running during reset.
PLLVSS
10 F
Figure 2.2
PLLVDD
and only connected at the
Output
Input
Input
Input
Input
2-11