L64105 LSI Logic Corporation, L64105 Datasheet - Page 147

• Manufacturer Part Number: L64105
• Description: Mpeg-2 Audio/video Decoder
• Manufacturer: LSI Logic Corporation

Figure 4.95
Figure 4.96
Correction
Automatic
Reserved
Inversion
Field
7
7
Pan and Scan
Bitstream
Register 278 (0x116)
Register 279 (0x117)
from
6
Main Reads per Line [6:0]
Reserved
Pan and Scan 1/8 Pixel Offset [2:0]
Pan and Scan Byte Offset [2:0]
Pan and Scan from Bitstream
Automatic Field Inversion Correction
Video Interface Registers
Pan and Scan Byte Offset [2:0]
5
This register is programmed with the number of reads
required to construct a scan line for display. The value
programmed is the number of pixels
number of display pixels may differ from main reads per
line because of the horizontal interpolation filter.
Clear this bit when writing to this register.
The subpixel offset of the first pixel on which the display
begins on each scan line.
The byte number within an 8-byte word on which the
display begins on each scan line.
When set to 1, this bit enables the decoder to decode the
pan and scan parameters from the bitstream. Clearing
this bit allows the host to specify the pan and scan 1/8
pixel and byte offsets.
When this bit is set, the display controller automatically
fixes any detected field inversions by displaying the next
frame starting at display line two in the frame store.
Main Reads per Line [6:0]
3
Pan and Scan 1/8 Pixel Offset [2:0]
2
8. Note that the
R/W [6:0]
R/W [2:0]
R/W [5:3]
R/W 6
R/W 7
0
0
4-65
7