L64105 LSI Logic Corporation, L64105 Datasheet - Page 148

• Manufacturer Part Number: L64105
• Description: Mpeg-2 Audio/video Decoder
• Manufacturer: LSI Logic Corporation

Figure 4.97
Figure 4.98
Figure 4.99
4-66
7
7
7
Register 280 (0x118) Horizontal Pan and Scan Luma/Chroma Word Offset
[7:0]
Register 281 (0x119) Vertical Pan and Scan Line Offset [7:0]
Register 282 (0x11A)
The word number on each scan line on which the display begins. Since
the Display Controller supports both positive and negative horizontal pan
and scan, this register only needs to apply an offset of up to
(720 pixels). These eight bits provide a signed (2’s complement) pan and
scan offset of
This register specifies the number of line pairs per field to pan vertically.
Vline Count Init [2:0]
Reserved
Register Descriptions
Horizontal Pan and Scan Luma/Chroma Word Offset [7:0]
Reserved
Vertical Pan and Scan Line Offset [7:0]
This field contains the value to which the vertical line
count initializes at the start of new field.
Clear these bits when writing to this register.
127 words.
R/W
R/W
3
2
Vline Count Init [2:0]
R/W [2:0]
90 words
0
0
0
[7:3]