L64105 LSI Logic Corporation, L64105 Datasheet - Page 91

• Manufacturer Part Number: L64105
• Description: Mpeg-2 Audio/video Decoder
• Manufacturer: LSI Logic Corporation

Figure 4.6
7
Reserved
Register 5 (0x005)
6
Reserved
Packet Error Interrupt
S/P DIF Channel Buffer Underflow Interrupt
Invert Channel Clock
Channel Request Mode
Host Interface Registers
VREQ
Status
5
Set these bits when writing to this register.
This bit is set and INTRn is asserted (if not masked)
when the preparser detects an error while processing
packet data. When this interrupt occurs, the host should
read the Packet Error Status register
determine in which packet the error occurred.
The Packet Error Interrupt bit is cleared when read.
INTRn is not asserted if the host sets the mask bit.
This bit is set and INTRn is asserted (if not masked)
when the S/P DIF read pointer in the Audio ES channel
buffer catches up to the write pointer (all buffer data read
to the S/P DIF Formatter).
The bit is cleared when read. INTRn is not asserted if the
host sets the mask bit.
When this bit is set, the internal DCK is inverted from the
external DCK clock. By default, the host interface accepts
the DCK and ACLK signals and ORs them together to
generate the internal VALID signal. This assumes that
channel data is available immediately after the rising
edge of DCK. For systems in which the data is available
immediately after the falling edge of DCK, this bit needs
to be set so that the internal VALID signal can be
generated on the falling edge of DCK. Asynchronous
systems can tie DCK to ground.
By default, the L64105 expects an external device to
sample the REQn (AREQn and VREQn) signals
synchronously with the system clock of the L64105. If the
external device requires the REQn signals to be
AREQ
Status
4
Channel
Bypass
Enable
3
Channel
Pause
2
Channel
Request
Mode
(page
1
4-37) to
Channel
Invert
Clock
R/W 0
R/W 1
0
[5:4]
4-9
6
7