L64105 LSI Logic Corporation, L64105 Datasheet - Page 294

• Manufacturer Part Number: L64105
• Description: Mpeg-2 Audio/video Decoder
• Manufacturer: LSI Logic Corporation

9.1 Overview
9-2
The Video Interface is shown in the block diagram of
includes postprocessing filters, mixers, and display control timing.
The Video Interface relies on a two-field display system operating with a
27-MHz pixel clock. The L64105 outputs 4:2:2 component video
compatible with the ITU-R BT.601 format, allowing data to be time-
division multiplexed onto an eight-bit bus. Eight-bit ITU-R BT.601 is the
preferred interface for professional quality video equipment.
The Address Generator, under control of the Timing Generator,
addresses the frame stores in SDRAM to read pixel data into the
postprocessing filters, reads display commands into the Display
Controller, and reads On-Screen Display (OSD) bitmap data into the
OSD Mixer. The postprocessing filters modify the pixel data on
instructions from the Display Controller for letterboxing, 3:2 pulldown, and
pan and scan.
The Display Controller also locates the video image with respect to the
sync signals to account for the requirements of several different timing
systems and display modes. The output of the filters passes through an
OSD Mixer that adds in the OSD information. The OSD Controller times
the OSD data and maintains the color palette.
The Display Controller provides a composite BLANK signal (horizontal
and vertical blanking) and a CREF signal to the NTSC/PAL Encoder.
CREF is high when a Cb byte is on the output bus.
Video Interface
Figure
9.1. It