UPD70F3738GF-GAS-AX Renesas Electronics America, UPD70F3738GF-GAS-AX Datasheet - Page 909

• Manufacturer Part Number: UPD70F3738GF-GAS-AX
• Description: MCU 32BIT V850ES/JX3-L 100-LQFP
• Manufacturer: Renesas Electronics America
• Series: V850ES/Jx3-Lr

Specifications of UPD70F3738GF-GAS-AX

• Core Processor: RISC
• Core Size: 32-Bit
• Speed: 20MHz
• Connectivity: CSI, EBI/EMI, I²C, UART/USART
• Peripherals: DMA, LVD, PWM, WDT
• Number Of I /o: 84
• Program Memory Size: 256KB (256K x 8)
• Program Memory Type: FLASH
• Ram Size: 16K x 8
• Voltage - Supply (vcc/vdd): 2.2 V ~ 3.6 V
• Data Converters: A/D 12x10b; D/A 2x8b
• Oscillator Type: Internal
• Operating Temperature: -40°C ~ 85°C
• Package / Case: *
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Eeprom Size: -

30.4.3 Interface
V850ES/JG3-L. For details, refer to the PG-FP5 User’s Manual (U18865E).
FLMD0
FLMD1
VDD
GND
CLK
RESET
SI/RxD
SO/TxD
SCK
HS
Signal Name
The dedicated flash memory programmer outputs the transfer clock, and the V850ES/JG3-L operates as a slave.
When the PG-FP5 is used as the dedicated flash memory programmer, it generates the following signals for the
Notes 1. For off-board programming, wire these pins as shown in Figures 30-6 and 30-7, or connect them to GND
Remark
2. To supply a clock to the V850ES/JG3-L, mount an oscillator on the board, or connect the CLK signal of
via a pull-down resistor on board. For on-board programming, wire these pins as shown in Figure 30-12.
the PG-FP5 with the X1 signal of the V850ES/JG3-L.
×: Does not have to be connected.
Output
Output
Output
Output
Input
Output
Output
Input
Table 30-5. Signal Connections of Dedicated Flash Memory Programmer (PG-FP5)
: Must be connected.
I/O
−
−
Write enable/disable
Write enable/disable
V
Ground
Clock output to V850ES/JG3-L
Reset signal
Receive signal
Transmit signal
Transfer clock
Handshake signal for CSIB0 + HS, CSIB3
+ HS communication
DD
PG-FP5
voltage generation/voltage monitor
Pin Function
CHAPTER 30 FLASH MEMORY
User’s Manual U18953EJ5V0UD
FLMD0
FLMD1
V
V
X1, X2
RESET
SOB0, SOB3/
TXDA0
SIB0, SIB3/
RXDA0
SCKB0, SCKB3
PCM0
V850ES/JG3-L
DD
SS
Pin Name
UARTA0
×
Note 2
×
×
Note 1
Processing for Connection
CSIB0,
CSIB3
×
Note 2
Note 1
×
CSIB0 + HS,
CSIB3 + HS
×
Note 2
Note 1
907