UPD70F3738GF-GAS-AX Renesas Electronics America, UPD70F3738GF-GAS-AX Datasheet - Page 50

• Manufacturer Part Number: UPD70F3738GF-GAS-AX
• Description: MCU 32BIT V850ES/JX3-L 100-LQFP
• Manufacturer: Renesas Electronics America
• Series: V850ES/Jx3-Lr

Specifications of UPD70F3738GF-GAS-AX

• Core Processor: RISC
• Core Size: 32-Bit
• Speed: 20MHz
• Connectivity: CSI, EBI/EMI, I²C, UART/USART
• Peripherals: DMA, LVD, PWM, WDT
• Number Of I /o: 84
• Program Memory Size: 256KB (256K x 8)
• Program Memory Type: FLASH
• Ram Size: 16K x 8
• Voltage - Supply (vcc/vdd): 2.2 V ~ 3.6 V
• Data Converters: A/D 12x10b; D/A 2x8b
• Oscillator Type: Internal
• Operating Temperature: -40°C ~ 85°C
• Package / Case: *
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Eeprom Size: -

<R>
2.2
Notes 1.
Remark
48
P05/DRST
P10/ANO0,
P11/ANO1
P53/DDO
AD0 to AD15
A0 to A15
A16 to A21
WAIT
CLKOUT
WR0, WR1
RD
ASTB
HLDAK
HLDRQ
Other port pins
The operation states of pins in the various modes are described below.
Pin Name
10.
11.
Pin States
2.
3.
4.
5.
6.
7.
8.
9.
Duration until 1 ms elapses after the supply voltage reaches the operating supply voltage range (lower
limit) when the power is turned on.
Operates while an alternate function is operating.
In separate bus mode, the state of the pins in the idle state inserted after the T2 state is shown. In
multiplexed bus mode, the state of the pins in the idle state inserted after the T3 state is shown (only after
a read operation).
μ
Pulled down during external reset. During internal reset by the watchdog timer, clock monitor, etc., the
state of this pin differs according to the OCDM.OCDM0 bit setting.
Because the V
undefined.
DDO output is specified in the on-chip debug mode.
The bus control pins function alternately as port pins, so they are initialized to the input mode (port mode).
Operates even in the HALT mode, during DMA operation.
In separate bus mode: Hi-Z
In multiplexed bus mode: Undefined
In separate bus mode
Hi-Z: High impedance
Held: The state during the immediately preceding external bus cycle is held.
L:
H:
−:
PD70F3792, 70F3793 only.
When Power
Pulled down
Undefined
Low-level output
High-level output
Input without sampling (not acknowledged)
Is Turned
Hi-Z
On
Hi-Z
Note 1
Note 8
DD
(Except When
During Reset
and EV
Turned On)
down
Table 2-2. Pin Operation States in Various Modes
Power Is
Hi-Z
Hi-Z
Pulled
Hi-Z
Hi-Z
Note 7
Note 8
Note 5
DD
voltages are less than the minimum operating voltage, the pin status is
CHAPTER 2 PIN FUNCTIONS
Undefined
HALT Mode
Undefined
Operating
User’s Manual U18953EJ5V0UD
Notes 9, 10
Operating
H
Held
Held
Held
Held
Note 7
−
Notes 9, 11
Note 9
Note 9
Note 2
Sub-IDLE
Mode
IDLE1,
IDLE2,
Held
Held
Held
Held
Hi-Z
H
−
L
−
Note 2
Mode
STOP
Held
Held
Held
Hi-Z
Hi-Z
H
−
L
−
Note 2
Operating
State
Held
Held
Held
Held
Held
Idle
H
−
−
Note 3
Operating
Operating
Bus Hold
Held
Held
Held
Held
Hi-Z
Hi-Z
−
L
RTC Back up
mode
Undefined
Note 4
Note 6