UPD70F3738GF-GAS-AX Renesas Electronics America, UPD70F3738GF-GAS-AX Datasheet - Page 227

• Manufacturer Part Number: UPD70F3738GF-GAS-AX
• Description: MCU 32BIT V850ES/JX3-L 100-LQFP
• Manufacturer: Renesas Electronics America
• Series: V850ES/Jx3-Lr

Specifications of UPD70F3738GF-GAS-AX

• Core Processor: RISC
• Core Size: 32-Bit
• Speed: 20MHz
• Connectivity: CSI, EBI/EMI, I²C, UART/USART
• Peripherals: DMA, LVD, PWM, WDT
• Number Of I /o: 84
• Program Memory Size: 256KB (256K x 8)
• Program Memory Type: FLASH
• Ram Size: 16K x 8
• Voltage - Supply (vcc/vdd): 2.2 V ~ 3.6 V
• Data Converters: A/D 12x10b; D/A 2x8b
• Oscillator Type: Internal
• Operating Temperature: -40°C ~ 85°C
• Package / Case: *
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Eeprom Size: -

(3) Lock register (LOCKR)
Caution The LOCK register does not reflect the lock status of the PLL in real time. The set/clear
[Set conditions]
[Clear conditions]
• Upon system reset
• In IDLE2 or STOP mode
• Upon setting of PLL stop (clearing of PLLCTL.PLLON bit to 0)
• Upon stopping main clock and using CPU on subclock (setting of PCC.CK3 bit to 1 and setting of
• Upon overflow of oscillation stabilization time following reset release (OSTS register default time (see
• Upon oscillation stabilization timer overflow (time set by OSTS register) following STOP mode release,
• Upon PLL lockup time timer overflow (time set by PLLS register) when the PLLCTL.PLLON bit is changed
• After the setup time inserted upon release of the IDLE2 mode (time set by the OSTS register) has elapsed
The PLL locks the phase at a given frequency after the power is turned on or immediately after the STOP
mode is canceled. The time required for the frequency to stabilize is the lockup time (frequency stabilization
time). This state until the frequency stabilizes is called the lockup status, and the state in which the frequency
is stabilized is called the locked status.
The LOCKR register includes a LOCK bit that reflects the PLL frequency stabilization status.
This register is read-only, in 8-bit or 1-bit units.
Reset sets this register to 00H.
PCC.MCK bit to 1)
Note This register is set to 01H by reset and cleared to 00H after the reset has been released and the
CHAPTER 29 OPTION BYTE))
when the STOP mode was set in the PLL operating status
from 0 to 1
when the IDLE2 mode is set during PLL operation.
conditions are as follows.
oscillation stabilization time has elapsed.
LOCKR
After reset: 00H
Note
LOCK
0
1
0
Locked status
Unlocked status
R
0
CHAPTER 6 CLOCK GENERATOR
Address: FFFFF824H
User’s Manual U18953EJ5V0UD
0
0
PLL lock status check
0
0
0
LOCK
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