UPD70F3738GF-GAS-AX Renesas Electronics America, UPD70F3738GF-GAS-AX Datasheet - Page 808

• Manufacturer Part Number: UPD70F3738GF-GAS-AX
• Description: MCU 32BIT V850ES/JX3-L 100-LQFP
• Manufacturer: Renesas Electronics America
• Series: V850ES/Jx3-Lr

Specifications of UPD70F3738GF-GAS-AX

• Core Processor: RISC
• Core Size: 32-Bit
• Speed: 20MHz
• Connectivity: CSI, EBI/EMI, I²C, UART/USART
• Peripherals: DMA, LVD, PWM, WDT
• Number Of I /o: 84
• Program Memory Size: 256KB (256K x 8)
• Program Memory Type: FLASH
• Ram Size: 16K x 8
• Voltage - Supply (vcc/vdd): 2.2 V ~ 3.6 V
• Data Converters: A/D 12x10b; D/A 2x8b
• Oscillator Type: Internal
• Operating Temperature: -40°C ~ 85°C
• Package / Case: *
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Eeprom Size: -

21.4 Software Exception
21.4.1 Operation
routine.
handler address is 00000040H, and if the vector is 10H to 1FH, the handler address is 00000050H.
806
A software exception occurs when the CPU executes the TRAP instruction, and can always be acknowledged.
If a software exception occurs, the CPU performs the following processing and transfers control to the handler
<1> Saves the current PC to EIPC.
<2> Saves the current PSW to EIPSW.
<3> Writes an exception code to the lower 16 bits (EICC) of ECR (interrupt source).
<4> Sets the PSW.EP and PSW.ID bits to 1.
<5> Sets the handler address (00000040H or 00000050H) for the software exception to the PC and transfers
The processing of a software exception is shown below.
The handler address is determined by the TRAP instruction’s operand (vector). If the vector is 00H to 0FH, the
Note TRAP instruction format: TRAP vector (the vector is a value from 00H to 1FH.)
control.
CHAPTER 21 INTERRUPT SERVICING/EXCEPTION PROCESSING FUNCTION
CPU processing
Figure 21-9. Software Exception Processing
User’s Manual U18953EJ5V0UD
EIPC
EIPSW
ECR.EICC
PSW.EP
PSW.ID
PC
Exception processing
TRAP instruction
PC
PSW
Exception code
1
1
Handler address
Note