UPD70F3738GF-GAS-AX Renesas Electronics America, UPD70F3738GF-GAS-AX Datasheet - Page 794

• Manufacturer Part Number: UPD70F3738GF-GAS-AX
• Description: MCU 32BIT V850ES/JX3-L 100-LQFP
• Manufacturer: Renesas Electronics America
• Series: V850ES/Jx3-Lr

Specifications of UPD70F3738GF-GAS-AX

• Core Processor: RISC
• Core Size: 32-Bit
• Speed: 20MHz
• Connectivity: CSI, EBI/EMI, I²C, UART/USART
• Peripherals: DMA, LVD, PWM, WDT
• Number Of I /o: 84
• Program Memory Size: 256KB (256K x 8)
• Program Memory Type: FLASH
• Ram Size: 16K x 8
• Voltage - Supply (vcc/vdd): 2.2 V ~ 3.6 V
• Data Converters: A/D 12x10b; D/A 2x8b
• Oscillator Type: Internal
• Operating Temperature: -40°C ~ 85°C
• Package / Case: *
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Eeprom Size: -

21.3 Maskable Interrupts
maskable interrupt sources.
interrupt request signals are not acknowledged.
acknowledgment of interrupt request signals having a priority higher than that of the interrupt request signal currently
being serviced. Interrupt request signals with the same priority level cannot be nested.
21.3.1 Operation
control to the handler routine.
interrupt request signal generated while another interrupt is being serviced (while the PSW.NP bit is 1 or the PSW.ID
bit is 1) are held pending in the INTC. The cause of being held pending and the workaround are described below.
Remark
792
xxMK bit = 1
Another interrupt having higher priority is
being held pending
PSW.NP bit = 1 and PSW.ID bit = 1
Maskable interrupt request signals can be masked by interrupt control registers. The V850ES/JG3-L has 55
When an interrupt request signal has been acknowledged, interrupts are disabled (DI) and subsequent maskable
When the EI instruction is executed in an interrupt service routine, interrupts are enabled (EI), which enables
For details about multiple interrupts, see 21.6 Multiple Interrupt Servicing Control.
If a maskable interrupt request signal is generated, the CPU performs the following processing and transfers
A maskable interrupt request signal masked by the interrupt controller (INTC)(xxMK bit = 1) and a maskable
Figure 21-5 shows the servicing of maskable interrupts.
<1> Saves the current PC to EIPC.
<2> Saves the current PSW to EIPSW.
<3> Writes an exception code to the lower halfword of ECR (EICC).
<4> Sets the PSW.ID bit to 1 and clears the PSW.EP bit to 0.
<5> Loads the corresponding handler address to the PC and transfers control.
For details about the xxMK bit, see 21.3.4 Interrupt control register (xxICn).
Cause
CHAPTER 21 INTERRUPT SERVICING/EXCEPTION PROCESSING FUNCTION
Table 21-2. Maskable Interrupts Held Pending
Unmask the signal (clear xxMK bit to 0).
Wait for the servicing of the interrupt to end.
Set the NP bit to 0 and the ID bit to 1 by using the RETI and LDSR instructions.
User’s Manual U18953EJ5V0UD
Workaround