UPD70F3738GF-GAS-AX Renesas Electronics America, UPD70F3738GF-GAS-AX Datasheet - Page 657

• Manufacturer Part Number: UPD70F3738GF-GAS-AX
• Description: MCU 32BIT V850ES/JX3-L 100-LQFP
• Manufacturer: Renesas Electronics America
• Series: V850ES/Jx3-Lr

Specifications of UPD70F3738GF-GAS-AX

• Core Processor: RISC
• Core Size: 32-Bit
• Speed: 20MHz
• Connectivity: CSI, EBI/EMI, I²C, UART/USART
• Peripherals: DMA, LVD, PWM, WDT
• Number Of I /o: 84
• Program Memory Size: 256KB (256K x 8)
• Program Memory Type: FLASH
• Ram Size: 16K x 8
• Voltage - Supply (vcc/vdd): 2.2 V ~ 3.6 V
• Data Converters: A/D 12x10b; D/A 2x8b
• Oscillator Type: Internal
• Operating Temperature: -40°C ~ 85°C
• Package / Case: *
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Eeprom Size: -

INTCBnR signal
INTCBnT signal
CBnTSF bit
SCKBn pin
SOBn pin
(1) Write 00H to the CBnCTL1 register, and select communication type 1, communication clock (f
(2) Write 00H to the CBnCTL2 register, and set the transfer data length to 8 bits.
(3) Write C3H to the CBnCTL0 register, and select the transmission mode, MSB first, and continuous
(4) The CBnSTR.CBnTSF bit is set to 1 by writing the transmit data to the CBnTX register, and
(5) When transmission is started, output the serial clock to the SCKBn pin, and output the transmit data
(6) When transfer of the transmit data from the CBnTX register to the shift register is completed and
(7) To continue transmission, repeat the above steps from (4) after the INTCBnT signal is generated.
(8) When new transmit data is written to the CBnTX register before communication is complete, the next
(9) The transfer of the transmit data from the CBnTX register to the shift register is completed and the
(10) If the next transmit data is not written to the CBnTX register before transfer is complete, wait for the
(11) To disable transmission, clear the CBnCTL0.CBnPWR and CBnCTL0.CBnTXE bits to 0 after
Caution In continuous transmission mode, the reception complete interrupt request signal
Remark
Figure 18-18. Continuous Transfer Mode Operation Timing (Master Mode, Transmission Mode)
f
transfer mode at the same time as enabling the operation of the communication clock (f
transmission is started.
from the SOBn pin in synchronization with the serial clock.
writing to the CBnTX register is enabled, the transmission enable interrupt request signal (INTCBnT) is
generated.
communication is started following the completion of communication.
INTCBnT signal is generated. To end continuous transmission with the current transmission, do not
write to the CBnTX register.
CBnTSF bit to be cleared to 0 after completion of transfer.
confirming that the CBnTSF bit is set to 0.
XX
L
/2, and master mode.
(1)
(2)
(3)
(INTCBnR) is not generated.
n = 0 to 4
(4)
(5)
Bit 7
(6)
Bit 6
CHAPTER 18 CLOCKED SERIAL INTERFACE B (CSIB)
Bit 5
Bit 4
(7)
Bit 3
User’s Manual U18953EJ5V0UD
Bit 2
Bit 1
Bit 0
(8)
Bit 7
(9)
Bit 6
Bit 5 Bit 4
Bit 3
Bit 2
Bit 1
(10)
Bit 0
CCLK
(11)
).
CCLK
) =
655