UPD70F3738GF-GAS-AX Renesas Electronics America, UPD70F3738GF-GAS-AX Datasheet - Page 429

• Manufacturer Part Number: UPD70F3738GF-GAS-AX
• Description: MCU 32BIT V850ES/JX3-L 100-LQFP
• Manufacturer: Renesas Electronics America
• Series: V850ES/Jx3-Lr

Specifications of UPD70F3738GF-GAS-AX

• Core Processor: RISC
• Core Size: 32-Bit
• Speed: 20MHz
• Connectivity: CSI, EBI/EMI, I²C, UART/USART
• Peripherals: DMA, LVD, PWM, WDT
• Number Of I /o: 84
• Program Memory Size: 256KB (256K x 8)
• Program Memory Type: FLASH
• Ram Size: 16K x 8
• Voltage - Supply (vcc/vdd): 2.2 V ~ 3.6 V
• Data Converters: A/D 12x10b; D/A 2x8b
• Oscillator Type: Internal
• Operating Temperature: -40°C ~ 85°C
• Package / Case: *
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Eeprom Size: -

Figure 8-61. Example of Resolving Problem When Two or More Capture Registers Are Used by Using
Note The TQ0OVF0 and TQ0OVF1 flags are set on the internal RAM by software.
<1> The TQ0CCR0 register is read (the default value of the TIQ00 pin input is set).
<2> The TQ0CCR1 register is read (the default value of the TIQ01 pin input is set).
<3> An overflow occurs. The TQ0OVF0 and TQ0OVF1 flags are set to 1 in the overflow interrupt
<4> The TQ0CCR0 register is read.
<5> The TQ0CCR1 register is read.
<6> Same as <3>.
TQ0CCR0 register
TQ0CCR1 register
INTTQ0OV signal
TQ0OVF0 flag
TQ0OVF1 flag
servicing, and the TQ0OVF bit is cleared to 0.
The TQ0OVF0 flag is read. The TQ0OVF0 flag is 1, so it is cleared to 0.
Because the TQ0OVF0 flag was 1, the pulse width can be calculated by (10000H + D
The TQ0OVF1 flag is read. The TQ0OVF1 flag is 1, so it is cleared to 0 (the TQ0OVF0 flag was
cleared in <4>; the TQ0OVF1 flag remained 1).
Because the TQ0OVF1 flag is 1, the pulse width can be calculated by (10000H + D
(correct).
TIQ00 pin input
TIQ01 pin input
16-bit counter
TQ0OVF bit
TQ0CE bit
FFFFH
0000H
Note
Note
CHAPTER 8 16-BIT TIMER/EVENT COUNTER Q (TMQ)
D
00
User’s Manual U18953EJ5V0UD
<1>
Overflow Interrupt
D
10
<2>
D
00
<3>
D
D
01
10
<4>
D
11
<5> <6>
D
01
D
11
01
− D
11
00
− D
).
10
)
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