UPD70F3738GF-GAS-AX Renesas Electronics America, UPD70F3738GF-GAS-AX Datasheet - Page 323

• Manufacturer Part Number: UPD70F3738GF-GAS-AX
• Description: MCU 32BIT V850ES/JX3-L 100-LQFP
• Manufacturer: Renesas Electronics America
• Series: V850ES/Jx3-Lr

Specifications of UPD70F3738GF-GAS-AX

• Core Processor: RISC
• Core Size: 32-Bit
• Speed: 20MHz
• Connectivity: CSI, EBI/EMI, I²C, UART/USART
• Peripherals: DMA, LVD, PWM, WDT
• Number Of I /o: 84
• Program Memory Size: 256KB (256K x 8)
• Program Memory Type: FLASH
• Ram Size: 16K x 8
• Voltage - Supply (vcc/vdd): 2.2 V ~ 3.6 V
• Data Converters: A/D 12x10b; D/A 2x8b
• Oscillator Type: Internal
• Operating Temperature: -40°C ~ 85°C
• Package / Case: *
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Eeprom Size: -

valid edge has been input to the TIPna pin, the value of the 16-bit counter is stored in the TPnCCRa register, the 16-
bit counter is cleared to 0000H, and a capture interrupt request signal (INTTPnCCa) is generated.
overflow interrupt request signal (INTTPnOV) is generated at the next count clock, and the counter is cleared to
0000H and continues incrementing. At this time, the overflow flag (TPnOPT0.TPnOVF bit) is also set to 1. Clear the
overflow flag to 0 by executing the software instruction CLR1.
When the TPnCE bit is set to 1, the 16-bit counter starts incrementing. When it is subsequently detected that a
The pulse width is calculated as follows.
If a valid edge has not been input to the TIPna pin by the time the 16-bit counter has incremented up to FFFFH, an
If the overflow flag is set to 1, the pulse width can be calculated as follows.
Remark
Pulse width = Captured value × Count clock cycle
Pulse width = (10000H × Number of times the TPnOVF bit was set (1) + Captured value) × Count clock cycle
INTTPnCCa signal
TPnCCRa register
INTTPnOV signal
TIPna pin input
a = 0, 1
n = 0 to 5
16-bit counter
TPnOVF bit
TPnCE bit
Figure 7-66. Basic Timing of Operations in Pulse Width Measurement Mode
FFFFH
0000H
CHAPTER 7 16-BIT TIMER/EVENT COUNTER P (TMP)
0000H
User’s Manual U18953EJ5V0UD
D
0
D
1
Cleared to 0 by
CLR1 instruction
D
2
D
3
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