UPD70F3738GF-GAS-AX Renesas Electronics America, UPD70F3738GF-GAS-AX Datasheet - Page 603

• Manufacturer Part Number: UPD70F3738GF-GAS-AX
• Description: MCU 32BIT V850ES/JX3-L 100-LQFP
• Manufacturer: Renesas Electronics America
• Series: V850ES/Jx3-Lr

Specifications of UPD70F3738GF-GAS-AX

• Core Processor: RISC
• Core Size: 32-Bit
• Speed: 20MHz
• Connectivity: CSI, EBI/EMI, I²C, UART/USART
• Peripherals: DMA, LVD, PWM, WDT
• Number Of I /o: 84
• Program Memory Size: 256KB (256K x 8)
• Program Memory Type: FLASH
• Ram Size: 16K x 8
• Voltage - Supply (vcc/vdd): 2.2 V ~ 3.6 V
• Data Converters: A/D 12x10b; D/A 2x8b
• Oscillator Type: Internal
• Operating Temperature: -40°C ~ 85°C
• Package / Case: *
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Eeprom Size: -

17.5 Interrupt Request Signals
transmission enable interrupt request signal.
The following two interrupt request signals are generated from UARTC0.
• Reception complete interrupt request signal (INTUC0R)
• Transmission enable interrupt request signal (INTUC0T)
The default priority for these two interrupt request signals is reception complete interrupt request signal then
(1) Reception complete interrupt request signal (INTUC0R)
(2) Transmission enable interrupt request signal (INTUC0T)
When the data stored in the receive shift register is transferred to the UC0RX register with reception enabled,
the reception complete interrupt request signal is generated.
A reception complete interrupt request signal is also output when a reception error occurs. Therefore, when a
reception complete interrupt request signal is acknowledged and the data is read, read the UC0STR register
and check that the reception result is not an error.
No reception complete interrupt request signal is generated in the reception disabled status.
If transmit data is transferred from the UC0TX register to the UARTC0 transmit shift register with transmission
enabled, the transmission enable interrupt request signal is generated.
CHAPTER 17 ASYNCHRONOUS SERIAL INTERFACE C (UARTC) (
Table 17-4. Interrupts and Their Default Priorities
Reception complete
Transmission enable
Interrupt Request Signal
User’s Manual U18953EJ5V0UD
Priority
High
Low
PD70F3792, 70F3793)
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