UPD70F3738GF-GAS-AX Renesas Electronics America, UPD70F3738GF-GAS-AX Datasheet - Page 679

• Manufacturer Part Number: UPD70F3738GF-GAS-AX
• Description: MCU 32BIT V850ES/JX3-L 100-LQFP
• Manufacturer: Renesas Electronics America
• Series: V850ES/Jx3-Lr

Specifications of UPD70F3738GF-GAS-AX

• Core Processor: RISC
• Core Size: 32-Bit
• Speed: 20MHz
• Connectivity: CSI, EBI/EMI, I²C, UART/USART
• Peripherals: DMA, LVD, PWM, WDT
• Number Of I /o: 84
• Program Memory Size: 256KB (256K x 8)
• Program Memory Type: FLASH
• Ram Size: 16K x 8
• Voltage - Supply (vcc/vdd): 2.2 V ~ 3.6 V
• Data Converters: A/D 12x10b; D/A 2x8b
• Oscillator Type: Internal
• Operating Temperature: -40°C ~ 85°C
• Package / Case: *
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Eeprom Size: -

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18.9 Cautions
(1)
(2)
(3) In communication type 2 or 4 (CBnCTL1.CBnDAP bit = 1), the CBnSTR.CBnTSF bit is cleared half a SCKBn
(4) The SIB1 and RXDC0 pins cannot be used at the same time. When using the pin for SIB1, stop UARTC0
Remark
clock cycle after occurrence of a reception complete interrupt (INTCBnR).
In the single transfer mode, writing the next transmit data is ignored during communication (CBnTSF bit = 1),
and the next communication is not started. Also if reception-only communication (CBnCTL0.CBnTXE bit = 0,
CBnCTL0.CBnRXE bit = 1) is set, the next communication is not started even if the receive data is read during
communication (CBnTSF bit = 1).
Therefore, when using the single transfer mode with communication type 2 or 4 (CBnDAP bit = 1), pay
particular attention to the following.
• To start the next transmission, confirm that the CBnTSF bit is 0 and then write the transmit data to the
• To perform the next reception continuously when reception-only communication (CBnTXE bit = 0, CBnRXE
Or, use the continuous transfer mode instead of the single transfer mode. Use of the continuous transfer mode
is recommended especially when using DMA.
reception. (clear the UC0CTL0.UC0RXE bit to 0.) When using the pin for RXDC0, stop CSIB0 reception. (clear
the CB1CTL0.CB1RXE bit to 0.)
When transferring transmit data and receive data using DMA transfer, error processing cannot be performed
even if an overrun error occurs during serial transfer. Check that the no overrun error has occurred by
reading the CBnSTR.CBnOVE bit after DMA transfer is complete.
In regards to registers that are forbidden must not be rewritten during operations (when the
CBnCTL0.CBnPWR bit is 1), if rewriting has been carried out by mistake, set the CBnCTL0.CBnPWR bit to 0
once, then initialize CSIBn.
The registers that must no be rewritten during operation are shown below.
• CBnCTL0 register: CBnTXE, CBnRXE, CBnDIR, CBnTMS bits
• CBnCTL1 register: CBnCKP, CBnDAP, CBnCKS2 to CBnCKS0 bits
• CBnCTL2 register: CBnCL3 to CBnCL0 bits
CBnTX register.
bit = 1) is set, confirm that the CBnTSF bit is 0 and then read the CBnRX register.
n = 0 to 4
CHAPTER 18 CLOCKED SERIAL INTERFACE B (CSIB)
User’s Manual U18953EJ5V0UD
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