UPD70F3738GF-GAS-AX Renesas Electronics America, UPD70F3738GF-GAS-AX Datasheet - Page 251

• Manufacturer Part Number: UPD70F3738GF-GAS-AX
• Description: MCU 32BIT V850ES/JX3-L 100-LQFP
• Manufacturer: Renesas Electronics America
• Series: V850ES/Jx3-Lr

Specifications of UPD70F3738GF-GAS-AX

• Core Processor: RISC
• Core Size: 32-Bit
• Speed: 20MHz
• Connectivity: CSI, EBI/EMI, I²C, UART/USART
• Peripherals: DMA, LVD, PWM, WDT
• Number Of I /o: 84
• Program Memory Size: 256KB (256K x 8)
• Program Memory Type: FLASH
• Ram Size: 16K x 8
• Voltage - Supply (vcc/vdd): 2.2 V ~ 3.6 V
• Data Converters: A/D 12x10b; D/A 2x8b
• Oscillator Type: Internal
• Operating Temperature: -40°C ~ 85°C
• Package / Case: *
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Eeprom Size: -

(1) Basic counter operation
The basic operation of the 16-bit counter is described below. For more details, see the descriptions of each
operating mode.
(a) Starting counting
(b) Clearing TMPn
(c) Overflow
(d) Reading TMPn while it is incrementing
TMPn starts counting from FFFFH in all operating modes, and increments as follows: FFFFH, 0000H,
0001H, 0002H, 0003H….
TMPn is cleared to 0000H when its value matches the value of the compare register or when the value of
TMPn is captured upon the input of a valid capture trigger signal.
Note that when TMPn increments from FFFFH to 0000H immediately after it starts counting and following
an overflow, it does not mean that TMPn has been cleared.
INTTPnCC1 interrupts are not generated in this case.
TMPn overflows after it increments from FFFFH to 0000H in free-running timer mode and pulse width
measurement mode. An overflow sets the TPnOPT0.TPnOVF bit to 1 and generates an interrupt request
signal (INTTPnOV). Note that INTTPnOV will not be generated in the following cases:
• When TMPn has just started counting.
• When the compare value at which TMPn is cleared is specified as FFFFH.
• In pulse width measurement mode, when TMPn increments from FFFFH to 0000H after being cleared
Caution After the INTTPnOV overflow interrupt request signal occurs, be sure to confirm that the
TMPn can be read while it is incrementing by using the TPnCNT register.
Specifically, the value of TMPn can be read by reading the TPnCNT register while the TPnCLT0.TPnCE bit
is 1. Note, however, that when the TPnCLT0.TPnCE bit is 0, the value of TMPn is always FFFFH and the
value of the TPnCNT register is always 0000H.
Remark
when its value of FFFFH was captured.
overflow flag (TPnOVF) is set to 1.
n = 0 to 5
CHAPTER 7 16-BIT TIMER/EVENT COUNTER P (TMP)
User’s Manual U18953EJ5V0UD
Consequently, the INTTPnCC0 and
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