UPD70F3738GF-GAS-AX Renesas Electronics America, UPD70F3738GF-GAS-AX Datasheet - Page 217

• Manufacturer Part Number: UPD70F3738GF-GAS-AX
• Description: MCU 32BIT V850ES/JX3-L 100-LQFP
• Manufacturer: Renesas Electronics America
• Series: V850ES/Jx3-Lr

Specifications of UPD70F3738GF-GAS-AX

• Core Processor: RISC
• Core Size: 32-Bit
• Speed: 20MHz
• Connectivity: CSI, EBI/EMI, I²C, UART/USART
• Peripherals: DMA, LVD, PWM, WDT
• Number Of I /o: 84
• Program Memory Size: 256KB (256K x 8)
• Program Memory Type: FLASH
• Ram Size: 16K x 8
• Voltage - Supply (vcc/vdd): 2.2 V ~ 3.6 V
• Data Converters: A/D 12x10b; D/A 2x8b
• Oscillator Type: Internal
• Operating Temperature: -40°C ~ 85°C
• Package / Case: *
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Eeprom Size: -

<R>
<R>
<R>
(1) Main clock oscillator
(2) Subclock oscillator
(3) Main clock oscillator stop control
(4) Internal oscillator
(5) Prescaler 1
(6) Prescaler 2
(7) PLL
(8) Clock I/O Circuit
The main clock oscillator uses a ceramic/crystal resonator connected to X1 and X2 pins to oscillate the
following frequencies (f
• In clock-through mode
• In PLL mode
An external clock of the following frequency is input to the X1 pin.
• In clock-through/PLL mode
The subclock oscillator oscillates a frequency of 32.768 kHz (f
In the
even in the RTC backup mode.
This circuit generates a control signal that stops oscillation of the main clock oscillator.
Oscillation of the main clock oscillator is stopped in the STOP mode or when the PCC.MCK bit is 1 (valid only
when the PCC.CLS bit is 1).
Oscillates a frequency (f
This prescaler generates the clock (f
TMP0 to TMP5, TMQ0, TMM0, CSIB0 to CSIB4, UARTA0 to UARTA5, UARTC0, I
WDT2
This circuit divides the main clock (f
The clock generated by prescaler 2 (f
(f
f
This circuit multiplies the clock generated by the main clock oscillator (f
It operates in two modes: clock-through mode in which f
clock is output. These modes can be selected by using the PLLCTL.SELPLL bit.
PLL is started or stopped by the PLLCTL.PLLON bit.
This circuit outputs the internal system clock to the CLKOUT pin.
The PMCCM1 bit of the PMCCM register for port CM controls whether the PMC1 pin operates as an I/O port or
as CLKOUT output.
CLK
CPU
f
f
f
X
X
X
is the clock supplied to the INTC, ROM, RAM, and DMA blocks, and can be output from the CLKOUT pin.
) and internal system clock (f
= 2.5 to 10 MHz (f
= 2.5 to 5 MHz (×4 : f
= 2.5 to 5 MHz
μ
PD70F3792,70F3793, this is in the RTC backup area and causes the subclock to continue oscillating
(f
XX
XX
X
).
R
= 1.25 to 10 MHz) (
) of 220 kHz (TYP.).
= 2.5 to 10 MHz) (
XX
= 10 to 20 MHz)
CLK
CHAPTER 6 CLOCK GENERATOR
XX
).
XX
).
User’s Manual U18953EJ5V0UD
to f
XX
to f
XX
μ
/1,024) to be supplied to the following on-chip peripheral functions:
μ
XX
PD70F3737, 70F3738)
PD70F3792, 70F3793)
/32) is supplied to the selector that generates the CPU clock
X
is output as is, and PLL mode in which a multiplied
XT
).
X
) by 4.
2
C00 to I
2
C02, ADC, and
215